Unverified Commit 40e7a399 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v5.16-rockchip-dts64-2' of... 

Merge tag 'v5.16-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

Idle-cooling information for rk3399, rk356x additions (tsadc resets,
i2s, spdif, pwm), rk3368 powerdomains, fixes to make gpio subnodes
compliant with the new pinctrl yaml binding and addition of the
chassis-type for the non-sbc devices.

* tag 'v5.16-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: Add idle cooling devices to rk3399
  arm64: dts: rockchip: fix resets in tsadc node for rk356x
  arm64: dts: rockchip: Add analog audio on Quartz64
  arm64: dts: rockchip: Add i2s1 on rk356x
  arm64: dts: rockchip: change gpio nodenames
  arm64: dts: rockchip: add 'chassis-type' property
  arm64: dts: rockchip: add powerdomains to rk3368
  dt-bindings: arm: rockchip: add rk3368 compatible string to pmu.yaml
  arm64: dts: rockchip: enable spdif on Quartz64 A
  arm64: dts: rockchip: add spdif node to rk356x
  arm64: dts: rockchip: add pwm nodes for rk3568

Link: https://lore.kernel.org/r/4536780.s7XYDJ6uuW@phil


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 7b27dc27 43f9699b

Documentation/devicetree/bindings/arm/rockchip/pmu.yaml

+2 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ select: 
          - rockchip,px30-pmu

          - rockchip,rk3066-pmu

          - rockchip,rk3288-pmu

          - rockchip,rk3368-pmu

          - rockchip,rk3399-pmu

          - rockchip,rk3568-pmu
@@ -35,6 +36,7 @@ properties: 
          - rockchip,px30-pmu

          - rockchip,rk3066-pmu

          - rockchip,rk3288-pmu

          - rockchip,rk3368-pmu

          - rockchip,rk3399-pmu

          - rockchip,rk3568-pmu

      - const: syscon

arch/arm64/boot/dts/rockchip/px30.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -1338,7 +1338,7 @@ pinctrl: pinctrl { 
		#size-cells = <2>;

		ranges;



		gpio0: gpio0@ff040000 {

		gpio0: gpio@ff040000 {

			compatible = "rockchip,gpio-bank";

			reg = <0x0 0xff040000 0x0 0x100>;

			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
@@ -1350,7 +1350,7 @@ gpio0: gpio0@ff040000 { 
			#interrupt-cells = <2>;

		};



		gpio1: gpio1@ff250000 {

		gpio1: gpio@ff250000 {

			compatible = "rockchip,gpio-bank";

			reg = <0x0 0xff250000 0x0 0x100>;

			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
@@ -1362,7 +1362,7 @@ gpio1: gpio1@ff250000 { 
			#interrupt-cells = <2>;

		};



		gpio2: gpio2@ff260000 {

		gpio2: gpio@ff260000 {

			compatible = "rockchip,gpio-bank";

			reg = <0x0 0xff260000 0x0 0x100>;

			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
@@ -1374,7 +1374,7 @@ gpio2: gpio2@ff260000 { 
			#interrupt-cells = <2>;

		};



		gpio3: gpio3@ff270000 {

		gpio3: gpio@ff270000 {

			compatible = "rockchip,gpio-bank";

			reg = <0x0 0xff270000 0x0 0x100>;

			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/rockchip/rk3308.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -790,7 +790,7 @@ pinctrl: pinctrl { 
		#size-cells = <2>;

		ranges;



		gpio0: gpio0@ff220000 {

		gpio0: gpio@ff220000 {

			compatible = "rockchip,gpio-bank";

			reg = <0x0 0xff220000 0x0 0x100>;

			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
@@ -801,7 +801,7 @@ gpio0: gpio0@ff220000 { 
			#interrupt-cells = <2>;

		};



		gpio1: gpio1@ff230000 {

		gpio1: gpio@ff230000 {

			compatible = "rockchip,gpio-bank";

			reg = <0x0 0xff230000 0x0 0x100>;

			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
@@ -812,7 +812,7 @@ gpio1: gpio1@ff230000 { 
			#interrupt-cells = <2>;

		};



		gpio2: gpio2@ff240000 {

		gpio2: gpio@ff240000 {

			compatible = "rockchip,gpio-bank";

			reg = <0x0 0xff240000 0x0 0x100>;

			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
@@ -823,7 +823,7 @@ gpio2: gpio2@ff240000 { 
			#interrupt-cells = <2>;

		};



		gpio3: gpio3@ff250000 {

		gpio3: gpio@ff250000 {

			compatible = "rockchip,gpio-bank";

			reg = <0x0 0xff250000 0x0 0x100>;

			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
@@ -834,7 +834,7 @@ gpio3: gpio3@ff250000 { 
			#interrupt-cells = <2>;

		};



		gpio4: gpio4@ff260000 {

		gpio4: gpio@ff260000 {

			compatible = "rockchip,gpio-bank";

			reg = <0x0 0xff260000 0x0 0x100>;

			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/rockchip/rk3328.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -1014,7 +1014,7 @@ pinctrl: pinctrl { 
		#size-cells = <2>;

		ranges;



		gpio0: gpio0@ff210000 {

		gpio0: gpio@ff210000 {

			compatible = "rockchip,gpio-bank";

			reg = <0x0 0xff210000 0x0 0x100>;

			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
@@ -1027,7 +1027,7 @@ gpio0: gpio0@ff210000 { 
			#interrupt-cells = <2>;

		};



		gpio1: gpio1@ff220000 {

		gpio1: gpio@ff220000 {

			compatible = "rockchip,gpio-bank";

			reg = <0x0 0xff220000 0x0 0x100>;

			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
@@ -1040,7 +1040,7 @@ gpio1: gpio1@ff220000 { 
			#interrupt-cells = <2>;

		};



		gpio2: gpio2@ff230000 {

		gpio2: gpio@ff230000 {

			compatible = "rockchip,gpio-bank";

			reg = <0x0 0xff230000 0x0 0x100>;

			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
@@ -1053,7 +1053,7 @@ gpio2: gpio2@ff230000 { 
			#interrupt-cells = <2>;

		};



		gpio3: gpio3@ff240000 {

		gpio3: gpio@ff240000 {

			compatible = "rockchip,gpio-bank";

			reg = <0x0 0xff240000 0x0 0x100>;

			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/rockchip/rk3368.dtsi

+182 −4
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/pinctrl/rockchip.h>

#include <dt-bindings/power/rk3368-power.h>

#include <dt-bindings/soc/rockchip,boot-mode.h>

#include <dt-bindings/thermal/thermal.h>
@@ -615,6 +616,115 @@ mbox: mbox@ff6b0000 { 
		status = "disabled";

	};



	pmu: power-management@ff730000 {

		compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";

		reg = <0x0 0xff730000 0x0 0x1000>;



		power: power-controller {

			compatible = "rockchip,rk3368-power-controller";

			#power-domain-cells = <1>;

			#address-cells = <1>;

			#size-cells = <0>;



			/*

			 * Note: Although SCLK_* are the working clocks

			 * of device without including on the NOC, needed for

			 * synchronous reset.

			 *

			 * The clocks on the which NOC:

			 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.

			 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.

			 * ACLK_RGA is on ACLK_RGA_NIU.

			 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.

			 *

			 * Which clock are device clocks:

			 *	clocks		devices

			 *	*_IEP		IEP:Image Enhancement Processor

			 *	*_ISP		ISP:Image Signal Processing

			 *	*_VIP		VIP:Video Input Processor

			 *	*_VOP*		VOP:Visual Output Processor

			 *	*_RGA		RGA

			 *	*_EDP*		EDP

			 *	*_DPHY*		LVDS

			 *	*_HDMI		HDMI

			 *	*_MIPI_*	MIPI

			 */

			power-domain@RK3368_PD_VIO {

				reg = <RK3368_PD_VIO>;

				clocks = <&cru ACLK_IEP>,

					 <&cru ACLK_ISP>,

					 <&cru ACLK_VIP>,

					 <&cru ACLK_RGA>,

					 <&cru ACLK_VOP>,

					 <&cru ACLK_VOP_IEP>,

					 <&cru DCLK_VOP>,

					 <&cru HCLK_IEP>,

					 <&cru HCLK_ISP>,

					 <&cru HCLK_RGA>,

					 <&cru HCLK_VIP>,

					 <&cru HCLK_VOP>,

					 <&cru HCLK_VIO_HDCPMMU>,

					 <&cru PCLK_EDP_CTRL>,

					 <&cru PCLK_HDMI_CTRL>,

					 <&cru PCLK_HDCP>,

					 <&cru PCLK_ISP>,

					 <&cru PCLK_VIP>,

					 <&cru PCLK_DPHYRX>,

					 <&cru PCLK_DPHYTX0>,

					 <&cru PCLK_MIPI_CSI>,

					 <&cru PCLK_MIPI_DSI0>,

					 <&cru SCLK_VOP0_PWM>,

					 <&cru SCLK_EDP_24M>,

					 <&cru SCLK_EDP>,

					 <&cru SCLK_HDCP>,

					 <&cru SCLK_ISP>,

					 <&cru SCLK_RGA>,

					 <&cru SCLK_HDMI_CEC>,

					 <&cru SCLK_HDMI_HDCP>;

				pm_qos = <&qos_iep>,

					 <&qos_isp_r0>,

					 <&qos_isp_r1>,

					 <&qos_isp_w0>,

					 <&qos_isp_w1>,

					 <&qos_vip>,

					 <&qos_vop>,

					 <&qos_rga_r>,

					 <&qos_rga_w>;

				#power-domain-cells = <0>;

			};



			/*

			 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC

			 * (video endecoder & decoder) clocks that on the

			 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).

			 */

			power-domain@RK3368_PD_VIDEO {

				reg = <RK3368_PD_VIDEO>;

				clocks = <&cru ACLK_VIDEO>,

					 <&cru HCLK_VIDEO>,

					 <&cru SCLK_HEVC_CABAC>,

					 <&cru SCLK_HEVC_CORE>;

				pm_qos = <&qos_hevc_r>,

					 <&qos_vpu_r>,

					 <&qos_vpu_w>;

				#power-domain-cells = <0>;

			};



			/*

			 * Note: ACLK_GPU is the GPU clock,

			 * and on the ACLK_GPU_NIU (NOC).

			 */

			power-domain@RK3368_PD_GPU_1 {

				reg = <RK3368_PD_GPU_1>;

				clocks = <&cru ACLK_GPU_CFG>,

					 <&cru ACLK_GPU_MEM>,

					 <&cru SCLK_GPU_CORE>;

				pm_qos = <&qos_gpu>;

				#power-domain-cells = <0>;

			};

		};

	};



	pmugrf: syscon@ff738000 {

		compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";

		reg = <0x0 0xff738000 0x0 0x1000>;
@@ -711,6 +821,7 @@ iep_mmu: iommu@ff900800 { 
		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;

		clock-names = "aclk", "iface";

		power-domains = <&power RK3368_PD_VIO>;

		#iommu-cells = <0>;

		status = "disabled";

	};
@@ -723,6 +834,7 @@ isp_mmu: iommu@ff914000 { 
		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;

		clock-names = "aclk", "iface";

		#iommu-cells = <0>;

		power-domains = <&power RK3368_PD_VIO>;

		rockchip,disable-mmu-reset;

		status = "disabled";

	};
@@ -733,6 +845,7 @@ vop_mmu: iommu@ff930300 { 
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;

		clock-names = "aclk", "iface";

		power-domains = <&power RK3368_PD_VIO>;

		#iommu-cells = <0>;

		status = "disabled";

	};
@@ -759,6 +872,71 @@ vpu_mmu: iommu@ff9a0800 { 
		status = "disabled";

	};



	qos_iep: qos@ffad0000 {

		compatible = "rockchip,rk3368-qos", "syscon";

		reg = <0x0 0xffad0000 0x0 0x20>;

	};



	qos_isp_r0: qos@ffad0080 {

		compatible = "rockchip,rk3368-qos", "syscon";

		reg = <0x0 0xffad0080 0x0 0x20>;

	};



	qos_isp_r1: qos@ffad0100 {

		compatible = "rockchip,rk3368-qos", "syscon";

		reg = <0x0 0xffad0100 0x0 0x20>;

	};



	qos_isp_w0: qos@ffad0180 {

		compatible = "rockchip,rk3368-qos", "syscon";

		reg = <0x0 0xffad0180 0x0 0x20>;

	};



	qos_isp_w1: qos@ffad0200 {

		compatible = "rockchip,rk3368-qos", "syscon";

		reg = <0x0 0xffad0200 0x0 0x20>;

	};



	qos_vip: qos@ffad0280 {

		compatible = "rockchip,rk3368-qos", "syscon";

		reg = <0x0 0xffad0280 0x0 0x20>;

	};



	qos_vop: qos@ffad0300 {

		compatible = "rockchip,rk3368-qos", "syscon";

		reg = <0x0 0xffad0300 0x0 0x20>;

	};



	qos_rga_r: qos@ffad0380 {

		compatible = "rockchip,rk3368-qos", "syscon";

		reg = <0x0 0xffad0380 0x0 0x20>;

	};



	qos_rga_w: qos@ffad0400 {

		compatible = "rockchip,rk3368-qos", "syscon";

		reg = <0x0 0xffad0400 0x0 0x20>;

	};



	qos_hevc_r: qos@ffae0000 {

		compatible = "rockchip,rk3368-qos", "syscon";

		reg = <0x0 0xffae0000 0x0 0x20>;

	};



	qos_vpu_r: qos@ffae0100 {

		compatible = "rockchip,rk3368-qos", "syscon";

		reg = <0x0 0xffae0100 0x0 0x20>;

	};



	qos_vpu_w: qos@ffae0180 {

		compatible = "rockchip,rk3368-qos", "syscon";

		reg = <0x0 0xffae0180 0x0 0x20>;

	};



	qos_gpu: qos@ffaf0000 {

		compatible = "rockchip,rk3368-qos", "syscon";

		reg = <0x0 0xffaf0000 0x0 0x20>;

	};



	efuse256: efuse@ffb00000 {

		compatible = "rockchip,rk3368-efuse";

		reg = <0x0 0xffb00000 0x0 0x20>;
@@ -797,7 +975,7 @@ pinctrl: pinctrl { 
		#size-cells = <0x2>;

		ranges;



		gpio0: gpio0@ff750000 {

		gpio0: gpio@ff750000 {

			compatible = "rockchip,gpio-bank";

			reg = <0x0 0xff750000 0x0 0x100>;

			clocks = <&cru PCLK_GPIO0>;
@@ -810,7 +988,7 @@ gpio0: gpio0@ff750000 { 
			#interrupt-cells = <0x2>;

		};



		gpio1: gpio1@ff780000 {

		gpio1: gpio@ff780000 {

			compatible = "rockchip,gpio-bank";

			reg = <0x0 0xff780000 0x0 0x100>;

			clocks = <&cru PCLK_GPIO1>;
@@ -823,7 +1001,7 @@ gpio1: gpio1@ff780000 { 
			#interrupt-cells = <0x2>;

		};



		gpio2: gpio2@ff790000 {

		gpio2: gpio@ff790000 {

			compatible = "rockchip,gpio-bank";

			reg = <0x0 0xff790000 0x0 0x100>;

			clocks = <&cru PCLK_GPIO2>;
@@ -836,7 +1014,7 @@ gpio2: gpio2@ff790000 { 
			#interrupt-cells = <0x2>;

		};



		gpio3: gpio3@ff7a0000 {

		gpio3: gpio@ff7a0000 {

			compatible = "rockchip,gpio-bank";

			reg = <0x0 0xff7a0000 0x0 0x100>;

			clocks = <&cru PCLK_GPIO3>;