Commit 4139fd58 authored by Thara Gopinath's avatar Thara Gopinath Committed by Herbert Xu
Browse files

crypto: qce - Remove totallen and offset in qce_start 



totallen is used to get the size of the data to be transformed.
This is also available via nbytes or cryptlen in the qce_sha_reqctx
and qce_cipher_ctx. Similarly offset convey nothing for the supported
encryption and authentication transformations and is always 0.
Remove these two redundant parameters in qce_start.

Reviewed-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: default avatarThara Gopinath <thara.gopinath@linaro.org>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 62e48428

drivers/crypto/qce/common.c

+7 −10
Original line number Diff line number Diff line
@@ -140,8 +140,7 @@ static u32 qce_auth_cfg(unsigned long flags, u32 key_size) 
	return cfg;

}



static int qce_setup_regs_ahash(struct crypto_async_request *async_req,

				u32 totallen, u32 offset)

static int qce_setup_regs_ahash(struct crypto_async_request *async_req)

{

	struct ahash_request *req = ahash_request_cast(async_req);

	struct crypto_ahash *ahash = __crypto_ahash_cast(async_req->tfm);
@@ -306,8 +305,7 @@ static void qce_xtskey(struct qce_device *qce, const u8 *enckey, 
	qce_write(qce, REG_ENCR_XTS_DU_SIZE, cryptlen);

}



static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,

				     u32 totallen, u32 offset)

static int qce_setup_regs_skcipher(struct crypto_async_request *async_req)

{

	struct skcipher_request *req = skcipher_request_cast(async_req);

	struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
@@ -367,7 +365,7 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req, 


	qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg);

	qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen);

	qce_write(qce, REG_ENCR_SEG_START, offset & 0xffff);

	qce_write(qce, REG_ENCR_SEG_START, 0);



	if (IS_CTR(flags)) {

		qce_write(qce, REG_CNTR_MASK, ~0);
@@ -376,7 +374,7 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req, 
		qce_write(qce, REG_CNTR_MASK2, ~0);

	}



	qce_write(qce, REG_SEG_SIZE, totallen);

	qce_write(qce, REG_SEG_SIZE, rctx->cryptlen);



	/* get little endianness */

	config = qce_config_reg(qce, 1);
@@ -388,17 +386,16 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req, 
}

#endif



int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen,

	      u32 offset)

int qce_start(struct crypto_async_request *async_req, u32 type)

{

	switch (type) {

#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER

	case CRYPTO_ALG_TYPE_SKCIPHER:

		return qce_setup_regs_skcipher(async_req, totallen, offset);

		return qce_setup_regs_skcipher(async_req);

#endif

#ifdef CONFIG_CRYPTO_DEV_QCE_SHA

	case CRYPTO_ALG_TYPE_AHASH:

		return qce_setup_regs_ahash(async_req, totallen, offset);

		return qce_setup_regs_ahash(async_req);

#endif

	default:

		return -EINVAL;

drivers/crypto/qce/common.h

+1 −2
Original line number Diff line number Diff line
@@ -94,7 +94,6 @@ struct qce_alg_template { 
void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len);

int qce_check_status(struct qce_device *qce, u32 *status);

void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step);

int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen,

	      u32 offset);

int qce_start(struct crypto_async_request *async_req, u32 type);



#endif /* _COMMON_H_ */

drivers/crypto/qce/sha.c

+1 −1
Original line number Diff line number Diff line
@@ -113,7 +113,7 @@ static int qce_ahash_async_req_handle(struct crypto_async_request *async_req) 


	qce_dma_issue_pending(&qce->dma);



	ret = qce_start(async_req, tmpl->crypto_alg_type, 0, 0);

	ret = qce_start(async_req, tmpl->crypto_alg_type);

	if (ret)

		goto error_terminate;

drivers/crypto/qce/skcipher.c

+1 −1
Original line number Diff line number Diff line
@@ -144,7 +144,7 @@ qce_skcipher_async_req_handle(struct crypto_async_request *async_req) 


	qce_dma_issue_pending(&qce->dma);



	ret = qce_start(async_req, tmpl->crypto_alg_type, req->cryptlen, 0);

	ret = qce_start(async_req, tmpl->crypto_alg_type);

	if (ret)

		goto error_terminate;