Commit 41d01f52 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
Browse files

clk: qcom: mmcc-apq8084: move clock parent tables down 



Move clock parent tables down, after the PLL declrataions, so that we
can use pll hw clock fields in the next commit.

Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230111060402.1168726-10-dmitry.baryshkov@linaro.org
parent 891feb0b

drivers/clk/qcom/mmcc-apq8084.c

+100 −100
Original line number Diff line number Diff line
@@ -40,6 +40,106 @@ enum { 
	P_MMSLEEP,

};



static struct clk_pll mmpll0 = {

	.l_reg = 0x0004,

	.m_reg = 0x0008,

	.n_reg = 0x000c,

	.config_reg = 0x0014,

	.mode_reg = 0x0000,

	.status_reg = 0x001c,

	.status_bit = 17,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "mmpll0",

		.parent_names = (const char *[]){ "xo" },

		.num_parents = 1,

		.ops = &clk_pll_ops,

	},

};



static struct clk_regmap mmpll0_vote = {

	.enable_reg = 0x0100,

	.enable_mask = BIT(0),

	.hw.init = &(struct clk_init_data){

		.name = "mmpll0_vote",

		.parent_names = (const char *[]){ "mmpll0" },

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,

	},

};



static struct clk_pll mmpll1 = {

	.l_reg = 0x0044,

	.m_reg = 0x0048,

	.n_reg = 0x004c,

	.config_reg = 0x0050,

	.mode_reg = 0x0040,

	.status_reg = 0x005c,

	.status_bit = 17,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "mmpll1",

		.parent_names = (const char *[]){ "xo" },

		.num_parents = 1,

		.ops = &clk_pll_ops,

	},

};



static struct clk_regmap mmpll1_vote = {

	.enable_reg = 0x0100,

	.enable_mask = BIT(1),

	.hw.init = &(struct clk_init_data){

		.name = "mmpll1_vote",

		.parent_names = (const char *[]){ "mmpll1" },

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,

	},

};



static struct clk_pll mmpll2 = {

	.l_reg = 0x4104,

	.m_reg = 0x4108,

	.n_reg = 0x410c,

	.config_reg = 0x4110,

	.mode_reg = 0x4100,

	.status_reg = 0x411c,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "mmpll2",

		.parent_names = (const char *[]){ "xo" },

		.num_parents = 1,

		.ops = &clk_pll_ops,

	},

};



static struct clk_pll mmpll3 = {

	.l_reg = 0x0084,

	.m_reg = 0x0088,

	.n_reg = 0x008c,

	.config_reg = 0x0090,

	.mode_reg = 0x0080,

	.status_reg = 0x009c,

	.status_bit = 17,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "mmpll3",

		.parent_names = (const char *[]){ "xo" },

		.num_parents = 1,

		.ops = &clk_pll_ops,

	},

};



static struct clk_pll mmpll4 = {

	.l_reg = 0x00a4,

	.m_reg = 0x00a8,

	.n_reg = 0x00ac,

	.config_reg = 0x00b0,

	.mode_reg = 0x0080,

	.status_reg = 0x00bc,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "mmpll4",

		.parent_names = (const char *[]){ "xo" },

		.num_parents = 1,

		.ops = &clk_pll_ops,

	},

};



static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {

	{ P_XO, 0 },

	{ P_MMPLL0, 1 },
@@ -212,106 +312,6 @@ static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = { 
	"sleep_clk_src",

};



static struct clk_pll mmpll0 = {

	.l_reg = 0x0004,

	.m_reg = 0x0008,

	.n_reg = 0x000c,

	.config_reg = 0x0014,

	.mode_reg = 0x0000,

	.status_reg = 0x001c,

	.status_bit = 17,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "mmpll0",

		.parent_names = (const char *[]){ "xo" },

		.num_parents = 1,

		.ops = &clk_pll_ops,

	},

};



static struct clk_regmap mmpll0_vote = {

	.enable_reg = 0x0100,

	.enable_mask = BIT(0),

	.hw.init = &(struct clk_init_data){

		.name = "mmpll0_vote",

		.parent_names = (const char *[]){ "mmpll0" },

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,

	},

};



static struct clk_pll mmpll1 = {

	.l_reg = 0x0044,

	.m_reg = 0x0048,

	.n_reg = 0x004c,

	.config_reg = 0x0050,

	.mode_reg = 0x0040,

	.status_reg = 0x005c,

	.status_bit = 17,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "mmpll1",

		.parent_names = (const char *[]){ "xo" },

		.num_parents = 1,

		.ops = &clk_pll_ops,

	},

};



static struct clk_regmap mmpll1_vote = {

	.enable_reg = 0x0100,

	.enable_mask = BIT(1),

	.hw.init = &(struct clk_init_data){

		.name = "mmpll1_vote",

		.parent_names = (const char *[]){ "mmpll1" },

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,

	},

};



static struct clk_pll mmpll2 = {

	.l_reg = 0x4104,

	.m_reg = 0x4108,

	.n_reg = 0x410c,

	.config_reg = 0x4110,

	.mode_reg = 0x4100,

	.status_reg = 0x411c,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "mmpll2",

		.parent_names = (const char *[]){ "xo" },

		.num_parents = 1,

		.ops = &clk_pll_ops,

	},

};



static struct clk_pll mmpll3 = {

	.l_reg = 0x0084,

	.m_reg = 0x0088,

	.n_reg = 0x008c,

	.config_reg = 0x0090,

	.mode_reg = 0x0080,

	.status_reg = 0x009c,

	.status_bit = 17,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "mmpll3",

		.parent_names = (const char *[]){ "xo" },

		.num_parents = 1,

		.ops = &clk_pll_ops,

	},

};



static struct clk_pll mmpll4 = {

	.l_reg = 0x00a4,

	.m_reg = 0x00a8,

	.n_reg = 0x00ac,

	.config_reg = 0x00b0,

	.mode_reg = 0x0080,

	.status_reg = 0x00bc,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "mmpll4",

		.parent_names = (const char *[]){ "xo" },

		.num_parents = 1,

		.ops = &clk_pll_ops,

	},

};



static struct clk_rcg2 mmss_ahb_clk_src = {

	.cmd_rcgr = 0x5000,

	.hid_width = 5,