Commit 41f9f0bf authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman
Browse files

staging: comedi: ni_stc.h: tidy up NI_M_AI_CFG_BYPASS_FIFO_REG bits 



Rename the CamelCase and convert the enum into defines. Use the BIT()
macro to define the bits. Convert the inline helper functions into
macros.

Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent b1c70645

drivers/staging/comedi/drivers/ni_mio_common.c

+9 −18
Original line number Diff line number Diff line
@@ -1763,22 +1763,17 @@ static void ni_m_series_load_channelgain_list(struct comedi_device *dev, 
		range = CR_RANGE(list[0]);

		range_code = ni_gainlkup[board->gainlkup][range];

		dither = (list[0] & CR_ALT_FILTER) != 0;

		bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;

		bypass_bits |= chan;

		bypass_bits |=

		    (devpriv->ai_calib_source) &

		    (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |

		     MSeries_AI_Bypass_Cal_Sel_Neg_Mask |

		     MSeries_AI_Bypass_Mode_Mux_Mask |

		     MSeries_AO_Bypass_AO_Cal_Sel_Mask);

		bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);

		bypass_bits = NI_M_CFG_BYPASS_FIFO |

			      NI_M_CFG_BYPASS_AI_CHAN(chan) |

			      NI_M_CFG_BYPASS_AI_GAIN(range_code) |

			      devpriv->ai_calib_source;

		if (dither)

			bypass_bits |= MSeries_AI_Bypass_Dither_Bit;

			bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;

		/*  don't use 2's complement encoding */

		bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;

		ni_writel(dev, bypass_bits, NI_M_AI_CFG_BYPASS_FIFO_REG);

		bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;

		ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);

	} else {

		ni_writel(dev, 0, NI_M_AI_CFG_BYPASS_FIFO_REG);

		ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);

	}

	for (i = 0; i < n_chan; i++) {

		unsigned config_bits = 0;
@@ -2579,12 +2574,8 @@ static int ni_ai_insn_config(struct comedi_device *dev, 
	switch (data[0]) {

	case INSN_CONFIG_ALT_SOURCE:

		if (devpriv->is_m_series) {

			if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |

					MSeries_AI_Bypass_Cal_Sel_Neg_Mask |

					MSeries_AI_Bypass_Mode_Mux_Mask |

					MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {

			if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)

				return -EINVAL;

			}

			devpriv->ai_calib_source = data[1];

		} else if (devpriv->is_6143) {

			unsigned int calib_source;

drivers/staging/comedi/drivers/ni_stc.h

+21 −30
Original line number Diff line number Diff line
@@ -995,7 +995,27 @@ static const struct comedi_lrange range_ni_E_ao_ext; 
#define NI_M_PFI_OUT_SEL_REG(x)		(0x1d0 + ((x) * 2))

#define NI_M_PFI_DI_REG			0x1dc

#define NI_M_PFI_DO_REG			0x1de

#define NI_M_AI_CFG_BYPASS_FIFO_REG	0x218

#define NI_M_CFG_BYPASS_FIFO_REG	0x218

#define NI_M_CFG_BYPASS_FIFO		BIT(31)

#define NI_M_CFG_BYPASS_AI_POLARITY	BIT(22)

#define NI_M_CFG_BYPASS_AI_DITHER	BIT(21)

#define NI_M_CFG_BYPASS_AI_GAIN(x)	(((x) & 0x7) << 18)

#define NI_M_CFG_BYPASS_AO_CAL(x)	(((x) & 0xf) << 15)

#define NI_M_CFG_BYPASS_AO_CAL_MASK	NI_M_CFG_BYPASS_AO_CAL(0xf)

#define NI_M_CFG_BYPASS_AI_MODE_MUX(x)	(((x) & 0x3) << 13)

#define NI_M_CFG_BYPASS_AI_MODE_MUX_MASK NI_M_CFG_BYPASS_AI_MODE_MUX(3)

#define NI_M_CFG_BYPASS_AI_CAL_NEG(x)	(((x) & 0x7) << 10)

#define NI_M_CFG_BYPASS_AI_CAL_NEG_MASK	NI_M_CFG_BYPASS_AI_CAL_NEG(7)

#define NI_M_CFG_BYPASS_AI_CAL_POS(x)	(((x) & 0x7) << 7)

#define NI_M_CFG_BYPASS_AI_CAL_POS_MASK	NI_M_CFG_BYPASS_AI_CAL_POS(7)

#define NI_M_CFG_BYPASS_AI_CAL_MASK	(NI_M_CFG_BYPASS_AI_CAL_POS_MASK | \

					 NI_M_CFG_BYPASS_AI_CAL_NEG_MASK | \

					 NI_M_CFG_BYPASS_AI_MODE_MUX_MASK | \

					 NI_M_CFG_BYPASS_AO_CAL_MASK)

#define NI_M_CFG_BYPASS_AI_BANK(x)	(((x) & 0xf) << 3)

#define NI_M_CFG_BYPASS_AI_BANK_MASK	NI_M_CFG_BYPASS_AI_BANK(0xf)

#define NI_M_CFG_BYPASS_AI_CHAN(x)	(((x) & 0x7) << 0)

#define NI_M_CFG_BYPASS_AI_CHAN_MASK	NI_M_CFG_BYPASS_AI_CHAN(7)

#define NI_M_SCXI_DIO_ENA_REG		0x21c

#define NI_M_CDI_FIFO_DATA_REG		0x220

#define NI_M_CDO_FIFO_DATA_REG		0x220
@@ -1008,35 +1028,6 @@ static const struct comedi_lrange range_ni_E_ao_ext; 
#define NI_M_STATIC_AI_CTRL_REG(x)	((x) ? (0x260 + (x)) : 0x064)

#define NI_M_AO_REF_ATTENUATION_REG(x)	(0x264 + (x))



enum MSeries_AI_Config_FIFO_Bypass_Bits {

	MSeries_AI_Bypass_Channel_Mask = 0x7,

	MSeries_AI_Bypass_Bank_Mask = 0x78,

	MSeries_AI_Bypass_Cal_Sel_Pos_Mask = 0x380,

	MSeries_AI_Bypass_Cal_Sel_Neg_Mask = 0x1c00,

	MSeries_AI_Bypass_Mode_Mux_Mask = 0x6000,

	MSeries_AO_Bypass_AO_Cal_Sel_Mask = 0x38000,

	MSeries_AI_Bypass_Gain_Mask = 0x1c0000,

	MSeries_AI_Bypass_Dither_Bit = 0x200000,

	MSeries_AI_Bypass_Polarity_Bit = 0x400000,	/*  0 for 2's complement encoding */

	MSeries_AI_Bypass_Config_FIFO_Bit = 0x80000000

};

static inline unsigned MSeries_AI_Bypass_Cal_Sel_Pos_Bits(int

							  calibration_source)

{

	return (calibration_source << 7) & MSeries_AI_Bypass_Cal_Sel_Pos_Mask;

}



static inline unsigned MSeries_AI_Bypass_Cal_Sel_Neg_Bits(int

							  calibration_source)

{

	return (calibration_source << 10) & MSeries_AI_Bypass_Cal_Sel_Pos_Mask;

}



static inline unsigned MSeries_AI_Bypass_Gain_Bits(int gain)

{

	return (gain << 18) & MSeries_AI_Bypass_Gain_Mask;

}



enum MSeries_AO_Config_Bank_Bits {

	MSeries_AO_DAC_Offset_Select_Mask = 0x7,

	MSeries_AO_DAC_Offset_0V_Bits = 0x0,