diff --git a/Documentation/arm/sti/overview.txt b/Documentation/arm/sti/overview.txt
new file mode 100644
index 0000000000000000000000000000000000000000..1a4e93d6027f41bff05ea0f28754cc258a6f6e9f
--- /dev/null
+++ b/Documentation/arm/sti/overview.txt
@@ -0,0 +1,33 @@
+ STi ARM Linux Overview
+ ==========================
+
+Introduction
+------------
+
+ The ST Microelectronics Multimedia and Application Processors range of
+ CortexA9 System-on-Chip are supported by the 'STi' platform of
+ ARM Linux. Currently STiH415, STiH416 SOCs are supported with both
+ B2000 and B2020 Reference boards.
+
+
+ configuration
+ -------------
+
+ A generic configuration is provided for both STiH415/416, and can be used as the
+ default by
+ make stih41x_defconfig
+
+ Layout
+ ------
+ All the files for multiple machine families (STiH415, STiH416, and STiG125)
+ are located in the platform code contained in arch/arm/mach-sti
+
+ There is a generic board board-dt.c in the mach folder which support
+ Flattened Device Tree, which means, It works with any compatible board with
+ Device Trees.
+
+
+ Document Author
+ ---------------
+
+ Srinivas Kandagatla <srinivas.kandagatla@st.com>, (c) 2013 ST Microelectronics
diff --git a/Documentation/arm/sti/stih415-overview.txt b/Documentation/arm/sti/stih415-overview.txt
new file mode 100644
index 0000000000000000000000000000000000000000..1383e33f265df59d3b6790d391e203120a47416a
--- /dev/null
+++ b/Documentation/arm/sti/stih415-overview.txt
@@ -0,0 +1,12 @@
+ STiH415 Overview
+ ================
+
+Introduction
+------------
+
+ The STiH415 is the next generation of HD, AVC set-top box processors
+ for satellite, cable, terrestrial and IP-STB markets.
+
+ Features
+ - ARM Cortex-A9 1.0 GHz, dual-core CPU
+ - SATA2x2,USB 2.0x3, PCIe, Gbit Ethernet MACx2
diff --git a/Documentation/arm/sti/stih416-overview.txt b/Documentation/arm/sti/stih416-overview.txt
new file mode 100644
index 0000000000000000000000000000000000000000..558444c201c6e51ecf55259e4300b40f3b6c176c
--- /dev/null
+++ b/Documentation/arm/sti/stih416-overview.txt
@@ -0,0 +1,12 @@
+ STiH416 Overview
+ ================
+
+Introduction
+------------
+
+ The STiH416 is the next generation of HD, AVC set-top box processors
+ for satellite, cable, terrestrial and IP-STB markets.
+
+ Features
+ - ARM Cortex-A9 1.2 GHz dual core CPU
+ - SATA2x2,USB 2.0x3, PCIe, Gbit Ethernet MACx2
diff --git a/Documentation/devicetree/bindings/arm/nspire.txt b/Documentation/devicetree/bindings/arm/nspire.txt
new file mode 100644
index 0000000000000000000000000000000000000000..4d08518bd176f117b786e1e602f2577517570528
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/nspire.txt
@@ -0,0 +1,14 @@
+TI-NSPIRE calculators
+
+Required properties:
+- compatible: Compatible property value should contain "ti,nspire".
+ CX models should have "ti,nspire-cx"
+ Touchpad models should have "ti,nspire-tp"
+ Clickpad models should have "ti,nspire-clp"
+
+Example:
+
+/ {
+ model = "TI-NSPIRE CX";
+ compatible = "ti,nspire-cx";
+ ...
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
new file mode 100644
index 0000000000000000000000000000000000000000..9bcc4b1bff51c74b091c2decea3b134c2d34fdde
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -0,0 +1,201 @@
+* Samsung Exynos5420 Clock Controller
+
+The Exynos5420 clock controller generates and supplies clock to various
+controllers within the Exynos5420 SoC.
+
+Required Properties:
+
+- comptible: should be one of the following.
+ - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume.
+
+
+ [Core Clocks]
+
+ Clock ID
+ ----------------------------
+
+ fin_pll 1
+
+ [Clock Gate for Special Clocks]
+
+ Clock ID
+ ----------------------------
+ sclk_uart0 128
+ sclk_uart1 129
+ sclk_uart2 130
+ sclk_uart3 131
+ sclk_mmc0 132
+ sclk_mmc1 133
+ sclk_mmc2 134
+ sclk_spi0 135
+ sclk_spi1 136
+ sclk_spi2 137
+ sclk_i2s1 138
+ sclk_i2s2 139
+ sclk_pcm1 140
+ sclk_pcm2 141
+ sclk_spdif 142
+ sclk_hdmi 143
+ sclk_pixel 144
+ sclk_dp1 145
+ sclk_mipi1 146
+ sclk_fimd1 147
+ sclk_maudio0 148
+ sclk_maupcm0 149
+ sclk_usbd300 150
+ sclk_usbd301 151
+ sclk_usbphy300 152
+ sclk_usbphy301 153
+ sclk_unipro 154
+ sclk_pwm 155
+ sclk_gscl_wa 156
+ sclk_gscl_wb 157
+
+ [Peripheral Clock Gates]
+
+ Clock ID
+ ----------------------------
+
+ aclk66_peric 256
+ uart0 257
+ uart1 258
+ uart2 259
+ uart3 260
+ i2c0 261
+ i2c1 262
+ i2c2 263
+ i2c3 264
+ i2c4 265
+ i2c5 266
+ i2c6 267
+ i2c7 268
+ i2c_hdmi 269
+ tsadc 270
+ spi0 271
+ spi1 272
+ spi2 273
+ keyif 274
+ i2s1 275
+ i2s2 276
+ pcm1 277
+ pcm2 278
+ pwm 279
+ spdif 280
+ i2c8 281
+ i2c9 282
+ i2c10 283
+ aclk66_psgen 300
+ chipid 301
+ sysreg 302
+ tzpc0 303
+ tzpc1 304
+ tzpc2 305
+ tzpc3 306
+ tzpc4 307
+ tzpc5 308
+ tzpc6 309
+ tzpc7 310
+ tzpc8 311
+ tzpc9 312
+ hdmi_cec 313
+ seckey 314
+ mct 315
+ wdt 316
+ rtc 317
+ tmu 318
+ tmu_gpu 319
+ pclk66_gpio 330
+ aclk200_fsys2 350
+ mmc0 351
+ mmc1 352
+ mmc2 353
+ sromc 354
+ ufs 355
+ aclk200_fsys 360
+ tsi 361
+ pdma0 362
+ pdma1 363
+ rtic 364
+ usbh20 365
+ usbd300 366
+ usbd301 377
+ aclk400_mscl 380
+ mscl0 381
+ mscl1 382
+ mscl2 383
+ smmu_mscl0 384
+ smmu_mscl1 385
+ smmu_mscl2 386
+ aclk333 400
+ mfc 401
+ smmu_mfcl 402
+ smmu_mfcr 403
+ aclk200_disp1 410
+ dsim1 411
+ dp1 412
+ hdmi 413
+ aclk300_disp1 420
+ fimd1 421
+ smmu_fimd1 422
+ aclk166 430
+ mixer 431
+ aclk266 440
+ rotator 441
+ mdma1 442
+ smmu_rotator 443
+ smmu_mdma1 444
+ aclk300_jpeg 450
+ jpeg 451
+ jpeg2 452
+ smmu_jpeg 453
+ aclk300_gscl 460
+ smmu_gscl0 461
+ smmu_gscl1 462
+ gscl_wa 463
+ gscl_wb 464
+ gscl0 465
+ gscl1 466
+ clk_3aa 467
+ aclk266_g2d 470
+ sss 471
+ slim_sss 472
+ mdma0 473
+ aclk333_g2d 480
+ g2d 481
+ aclk333_432_gscl 490
+ smmu_3aa 491
+ smmu_fimcl0 492
+ smmu_fimcl1 493
+ smmu_fimcl3 494
+ fimc_lite3 495
+ aclk_g3d 500
+ g3d 501
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x10010000 {
+ compatible = "samsung,exynos5420-clock";
+ reg = <0x10010000 0x30000>;
+ #clock-cells = <1>;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@13820000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13820000 0x100>;
+ interrupts = <0 54 0>;
+ clocks = <&clock 259>, <&clock 130>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 72e9cd1e89b7a147938579f02e507a8728cd0d2e..36281e7a2a46189b2f52368da288c90021a4de17 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -15,6 +15,7 @@ Required Properties:
- "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
- "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
+ - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index d247d1003987b2ee1901103446035643587faa47..db0457d616822429faaefbda7773b13919495751 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -31,6 +31,7 @@ idt Integrated Device Technologies, Inc.
img Imagination Technologies Ltd.
intercontrol Inter Control Group
linux Linux-specific binding
+lsi LSI Corp. (LSI Logic)
marvell Marvell Technology Group Ltd.
maxim Maxim Integrated Products
mosaixtech Mosaix Technologies, Inc.
diff --git a/MAINTAINERS b/MAINTAINERS
index 8128b141b92bebcd97a93f617f6be0166d0ee8ad..e626794c3860d075f5339b3760b9edfa3b18d8b6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1203,6 +1203,15 @@ M: Dinh Nguyen <dinguyen@altera.com>
S: Maintained
F: drivers/clk/socfpga/
+ARM/STI ARCHITECTURE
+M: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+M: Stuart Menefy <stuart.menefy@st.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L: kernel@stlinux.com
+W: http://www.stlinux.com
+S: Maintained
+F: arch/arm/mach-sti/
+
ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 49fdc432512f572e985440a116188b69843faa80..de7049bdea857b291bab04b24362b50f096d68d7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -625,8 +625,8 @@ config ARCH_MSM
bool "Qualcomm MSM"
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
+ select COMMON_CLK
select GENERIC_CLOCKEVENTS
- select HAVE_CLK
help
Support for Qualcomm MSM/QSD based systems. This runs on the
apps processor of the MSM/QSD and depends on a shared memory
@@ -969,6 +969,8 @@ source "arch/arm/mach-netx/Kconfig"
source "arch/arm/mach-nomadik/Kconfig"
+source "arch/arm/mach-nspire/Kconfig"
+
source "arch/arm/plat-omap/Kconfig"
source "arch/arm/mach-omap1/Kconfig"
@@ -996,6 +998,8 @@ source "arch/arm/mach-socfpga/Kconfig"
source "arch/arm/mach-spear/Kconfig"
+source "arch/arm/mach-sti/Kconfig"
+
source "arch/arm/mach-s3c24xx/Kconfig"
if ARCH_S3C64XX
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index ab95f07e154131adb2faf54e5b72f8d1b8495c9a..77c1411c9a91ab04132a847e2403cc500dc5a25b 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -362,6 +362,20 @@ choice
Say Y here if you want kernel low-level debugging support
on NOMADIK based platforms.
+ config DEBUG_NSPIRE_CLASSIC_UART
+ bool "Kernel low-level debugging via TI-NSPIRE 8250 UART"
+ depends on ARCH_NSPIRE
+ help
+ Say Y here if you want kernel low-level debugging support
+ on TI-NSPIRE classic models.
+
+ config DEBUG_NSPIRE_CX_UART
+ bool "Kernel low-level debugging via TI-NSPIRE PL011 UART"
+ depends on ARCH_NSPIRE
+ help
+ Say Y here if you want kernel low-level debugging support
+ on TI-NSPIRE CX models.
+
config DEBUG_OMAP2PLUS_UART
bool "Kernel low-level debugging messages via OMAP2PLUS UART"
depends on ARCH_OMAP2PLUS
@@ -543,6 +557,16 @@ choice
This option selects UART0 on VIA/Wondermedia System-on-a-chip
devices, including VT8500, WM8505, WM8650 and WM8850.
+ config DEBUG_STI_UART
+ depends on ARCH_STI
+ bool "Use StiH415/416 ASC for low-level debug"
+ help
+ Say Y here if you want kernel low-level debugging support
+ on StiH415/416 based platforms like B2000, B2020.
+ It support UART2 and SBC_UART1.
+
+ If unsure, say N.
+
config DEBUG_LL_UART_NONE
bool "No low-level debugging UART"
depends on !ARCH_MULTIPLATFORM
@@ -704,6 +728,30 @@ choice
endchoice
+choice
+ prompt "Low-level debug console UART"
+ depends on DEBUG_LL && DEBUG_STI_UART
+
+ config STIH41X_DEBUG_ASC2
+ bool "ASC2 UART"
+ help
+ Say Y here if you want kernel low-level debugging support
+ on STiH415/416 based platforms like b2000, which has
+ default UART wired up to ASC2.
+
+ If unsure, say N.
+
+ config STIH41X_DEBUG_SBC_ASC1
+ bool "SBC ASC1 UART"
+ help
+ Say Y here if you want kernel low-level debugging support
+ on STiH415/416 based platforms like b2020. which has
+ default UART wired up to SBC ASC1.
+
+ If unsure, say N.
+
+endchoice
+
config DEBUG_LL_INCLUDE
string
default "debug/bcm2835.S" if DEBUG_BCM2835
@@ -726,6 +774,8 @@ config DEBUG_LL_INCLUDE
DEBUG_MVEBU_UART_ALTERNATE
default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART
default "debug/nomadik.S" if DEBUG_NOMADIK_UART
+ default "debug/nspire.S" if DEBUG_NSPIRE_CX_UART || \
+ DEBUG_NSPIRE_CLASSIC_UART
default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
default "debug/pxa.S" if DEBUG_PXA_UART1 || DEBUG_MMP_UART2 || \
@@ -733,6 +783,7 @@ config DEBUG_LL_INCLUDE
default "debug/rockchip.S" if DEBUG_ROCKCHIP_UART
default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
+ default "debug/sti.S" if DEBUG_STI_UART
default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
default "debug/tegra.S" if DEBUG_TEGRA_UART
default "debug/u300.S" if DEBUG_U300_UART
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c01e4a728554a79540041ec872df72af5154fc77..72caf82a8280c816e4517f05c9444261d77795b8 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -165,6 +165,7 @@ machine-$(CONFIG_ARCH_MXS) += mxs
machine-$(CONFIG_ARCH_MVEBU) += mvebu
machine-$(CONFIG_ARCH_NETX) += netx
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
+machine-$(CONFIG_ARCH_NSPIRE) += nspire
machine-$(CONFIG_ARCH_OMAP1) += omap1
machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
machine-$(CONFIG_ARCH_ORION5X) += orion5x
@@ -193,6 +194,7 @@ machine-$(CONFIG_ARCH_W90X900) += w90x900
machine-$(CONFIG_FOOTBRIDGE) += footbridge
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_PLAT_SPEAR) += spear
+machine-$(CONFIG_ARCH_STI) += sti
machine-$(CONFIG_ARCH_VIRT) += virt
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_ARCH_SUNXI) += sunxi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 962c0eee3039a02580f7feb59966370061c2e486..641b3c9a7028c3368b5502c4a0f229c99327e521 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -59,6 +59,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5440-sd5v1.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5420-smdk5420.dtb \
exynos5440-ssdk5440.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
ecx-2000.dtb
@@ -148,6 +149,9 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
imx28-sps1.dtb \
imx28-tx28.dtb
dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb
+dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \
+ nspire-tp.dtb \
+ nspire-clp.dtb
dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
omap3430-sdp.dtb \
omap3-beagle.dtb \
@@ -197,6 +201,10 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
spear320-evb.dtb \
spear320-hmi.dtb
dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
+dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \
+ stih416-b2000.dtb \
+ stih415-b2020.dtb \
+ stih416-b2020.dtb
dtb-$(CONFIG_ARCH_SUNXI) += \
sun4i-a10-cubieboard.dtb \
sun4i-a10-mini-xplus.dtb \
diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/da850-enbw-cmc.dts
index 422fdb3fcfc163544275af183299379993f14088..e750ab9086d50d73d1c07559fea2fc9c0fbf900d 100644
--- a/arch/arm/boot/dts/da850-enbw-cmc.dts
+++ b/arch/arm/boot/dts/da850-enbw-cmc.dts
@@ -10,7 +10,7 @@
* option) any later version.
*/
/dts-v1/;
-/include/ "da850.dtsi"
+#include "da850.dtsi"
/ {
compatible = "enbw,cmc", "ti,da850";
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index c914357c0d894c67a8d1a985e182d409f4ec68ce..5bce7cc55cf35ba6446ff77803f5aa167899aaea 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -8,7 +8,7 @@
* Free Software Foundation, version 2.
*/
/dts-v1/;
-/include/ "da850.dtsi"
+#include "da850.dtsi"
/ {
compatible = "ti,da850-evm", "ti,da850";
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 2c88313d2c7af6730772f4a4e53c8797fd6fda8d..d70ba5504481d90b796872d4c258061cb8de4b4d 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -7,7 +7,7 @@
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
/ {
arm {
@@ -37,7 +37,7 @@ pmx_core: pinmux@1c14120 {
#size-cells = <0>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
+ pinctrl-single,function-mask = <0xf>;
status = "disabled";
nand_cs3_pins: pinmux_nand_pins {
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..f65e124c04a6901699823d72b7f372a178377f92
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -0,0 +1,111 @@
+/*
+ * Samsung's Exynos5 SoC series common device tree source
+ *
+ * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular
+ * SoCs from Exynos5 series can include this file and provide values for SoCs
+ * specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+
+ chipid@10000000 {
+ compatible = "samsung,exynos4210-chipid";
+ reg = <0x10000000 0x100>;
+ };
+
+ combiner:interrupt-controller@10440000 {
+ compatible = "samsung,exynos4210-combiner";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ samsung,combiner-nr = <32>;
+ reg = <0x10440000 0x1000>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+ <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+ <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+ <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+ <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+ <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+ <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+ };
+
+ gic:interrupt-controller@10481000 {
+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x10481000 0x1000>,
+ <0x10482000 0x1000>,
+ <0x10484000 0x2000>,
+ <0x10486000 0x2000>;
+ interrupts = <1 9 0xf04>;
+ };
+
+ dwmmc_0: dwmmc0@12200000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 75 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ dwmmc_1: dwmmc1@12210000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 76 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ dwmmc_2: dwmmc2@12220000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 77 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ serial@12C00000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C00000 0x100>;
+ interrupts = <0 51 0>;
+ };
+
+ serial@12C10000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C10000 0x100>;
+ interrupts = <0 52 0>;
+ };
+
+ serial@12C20000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C20000 0x100>;
+ interrupts = <0 53 0>;
+ };
+
+ serial@12C30000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C30000 0x100>;
+ interrupts = <0 54 0>;
+ };
+
+ rtc {
+ compatible = "samsung,s3c6410-rtc";
+ reg = <0x101E0000 0x100>;
+ interrupts = <0 43 0>, <0 44 0>;
+ status = "disabled";
+ };
+
+ watchdog {
+ compatible = "samsung,s3c2410-wdt";
+ reg = <0x101D0000 0x100>;
+ interrupts = <0 42 0>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 964158c1844f5408c80dae93f1c579814218598e..41cd625b602039ce7a7a41f4dcc57bc589b81837 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -17,14 +17,13 @@
* published by the Free Software Foundation.
*/
-#include "skeleton.dtsi"
+#include "exynos5.dtsi"
#include "exynos5250-pinctrl.dtsi"
#include <dt-bindings/clk/exynos-audss-clk.h>
/ {
compatible = "samsung,exynos5250";
- interrupt-parent = <&gic>;
aliases {
spi0 = &spi_0;
@@ -53,9 +52,20 @@ aliases {
pinctrl3 = &pinctrl_3;
};
- chipid@10000000 {
- compatible = "samsung,exynos4210-chipid";
- reg = <0x10000000 0x100>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ };
};
pd_gsc: gsc-power-domain@0x10044000 {
@@ -80,17 +90,6 @@ clock_audss: audss-clock-controller@3810000 {
#clock-cells = <1>;
};
- gic:interrupt-controller@10481000 {
- compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x10481000 0x1000>,
- <0x10482000 0x1000>,
- <0x10484000 0x2000>,
- <0x10486000 0x2000>;
- interrupts = <1 9 0xf04>;
- };
-
timer {
compatible = "arm,armv7-timer";
interrupts = <1 13 0xf08>,
@@ -99,22 +98,6 @@ timer {
<1 10 0xf08>;
};
- combiner:interrupt-controller@10440000 {
- compatible = "samsung,exynos4210-combiner";
- #interrupt-cells = <2>;
- interrupt-controller;
- samsung,combiner-nr = <32>;
- reg = <0x10440000 0x1000>;
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
- <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
- <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
- <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
- <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
- <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
- };
-
mct@101C0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x101C0000 0x800>;
@@ -176,9 +159,6 @@ pinctrl_3: pinctrl@03860000 {
};
watchdog {
- compatible = "samsung,s3c2410-wdt";
- reg = <0x101D0000 0x100>;
- interrupts = <0 42 0>;
clocks = <&clock 336>;
clock-names = "watchdog";
};
@@ -191,12 +171,8 @@ codec@11000000 {
};
rtc {
- compatible = "samsung,s3c6410-rtc";
- reg = <0x101E0000 0x100>;
- interrupts = <0 43 0>, <0 44 0>;
clocks = <&clock 337>;
clock-names = "rtc";
- status = "disabled";
};
tmu@10060000 {
@@ -208,33 +184,21 @@ tmu@10060000 {
};
serial@12C00000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C00000 0x100>;
- interrupts = <0 51 0>;
clocks = <&clock 289>, <&clock 146>;
clock-names = "uart", "clk_uart_baud0";
};
serial@12C10000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C10000 0x100>;
- interrupts = <0 52 0>;
clocks = <&clock 290>, <&clock 147>;
clock-names = "uart", "clk_uart_baud0";
};
serial@12C20000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C20000 0x100>;
- interrupts = <0 53 0>;
clocks = <&clock 291>, <&clock 148>;
clock-names = "uart", "clk_uart_baud0";
};
serial@12C30000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C30000 0x100>;
- interrupts = <0 54 0>;
clocks = <&clock 292>, <&clock 149>;
clock-names = "uart", "clk_uart_baud0";
};
@@ -413,31 +377,19 @@ spi_2: spi@12d40000 {
};
dwmmc_0: dwmmc0@12200000 {
- compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12200000 0x1000>;
- interrupts = <0 75 0>;
- #address-cells = <1>;
- #size-cells = <0>;
clocks = <&clock 280>, <&clock 139>;
clock-names = "biu", "ciu";
};
dwmmc_1: dwmmc1@12210000 {
- compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12210000 0x1000>;
- interrupts = <0 76 0>;
- #address-cells = <1>;
- #size-cells = <0>;
clocks = <&clock 281>, <&clock 140>;
clock-names = "biu", "ciu";
};
dwmmc_2: dwmmc2@12220000 {
- compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12220000 0x1000>;
- interrupts = <0 77 0>;
- #address-cells = <1>;
- #size-cells = <0>;
clocks = <&clock 282>, <&clock 141>;
clock-names = "biu", "ciu";
};
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..5848c425ae4d40fcb1c9edd46dfef3827df2f193
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -0,0 +1,680 @@
+/*
+ * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+ pinctrl@13400000 {
+ gpy7: gpy7 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx0: gpx0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&combiner>;
+ #interrupt-cells = <2>;
+ interrupts = <23 0>, <24 0>, <25 0>, <25 1>,
+ <26 0>, <26 1>, <27 0>, <27 1>;
+ };
+
+ gpx1: gpx1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&combiner>;
+ #interrupt-cells = <2>;
+ interrupts = <28 0>, <28 1>, <29 0>, <29 1>,
+ <30 0>, <30 1>, <31 0>, <31 1>;
+ };
+
+ gpx2: gpx2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx3: gpx3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pinctrl@13410000 {
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc2: gpc2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc3: gpc3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc4: gpc4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpy0: gpy0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy1: gpy1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy2: gpy2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy3: gpy3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy4: gpy4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy5: gpy5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy6: gpy6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ sd0_clk: sd0-clk {
+ samsung,pins = "gpc0-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_cmd: sd0-cmd {
+ samsung,pins = "gpc0-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_cd: sd0-cd {
+ samsung,pins = "gpc0-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_bus1: sd0-bus-width1 {
+ samsung,pins = "gpc0-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_bus4: sd0-bus-width4 {
+ samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_bus8: sd0-bus-width8 {
+ samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_clk: sd1-clk {
+ samsung,pins = "gpc1-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_cmd: sd1-cmd {
+ samsung,pins = "gpc1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_cd: sd1-cd {
+ samsung,pins = "gpc1-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_int: sd1-int {
+ samsung,pins = "gpd1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd1_bus1: sd1-bus-width1 {
+ samsung,pins = "gpc1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_bus4: sd1-bus-width4 {
+ samsung,pins = "gpc1-4", "gpc1-5", "gpc1-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_bus8: sd1-bus-width8 {
+ samsung,pins = "gpd1-4", "gpd1-5", "gpd1-6", "gpd1-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_clk: sd2-clk {
+ samsung,pins = "gpc2-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_cmd: sd2-cmd {
+ samsung,pins = "gpc2-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_cd: sd2-cd {
+ samsung,pins = "gpc2-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_bus1: sd2-bus-width1 {
+ samsung,pins = "gpc2-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_bus4: sd2-bus-width4 {
+ samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+ };
+
+ pinctrl@14000000 {
+ gpe0: gpe0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe1: gpe1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf1: gpf1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg0: gpg0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg1: gpg1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg2: gpg2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpj4: gpj4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ cam_gpio_a: cam-gpio-a {
+ samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
+ "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
+ "gpe1-0", "gpe1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ cam_gpio_b: cam-gpio-b {
+ samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3",
+ "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ cam_i2c2_bus: cam-i2c2-bus {
+ samsung,pins = "gpf0-4", "gpf0-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+ cam_spi1_bus: cam-spi1-bus {
+ samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ cam_i2c1_bus: cam-i2c1-bus {
+ samsung,pins = "gpf0-2", "gpf0-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ cam_i2c0_bus: cam-i2c0-bus {
+ samsung,pins = "gpf0-0", "gpf0-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ cam_spi0_bus: cam-spi0-bus {
+ samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ cam_bayrgb_bus: cam-bayrgb-bus {
+ samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3",
+ "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7",
+ "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3",
+ "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7",
+ "gpg2-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+ };
+
+ pinctrl@14010000 {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb1: gpb1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb2: gpb2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb3: gpb3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb4: gpb4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gph0: gph0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ uart0_data: uart0-data {
+ samsung,pins = "gpa0-0", "gpa0-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart0_fctl: uart0-fctl {
+ samsung,pins = "gpa0-2", "gpa0-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart1_data: uart1-data {
+ samsung,pins = "gpa0-4", "gpa0-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart1_fctl: uart1-fctl {
+ samsung,pins = "gpa0-6", "gpa0-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c2_bus: i2c2-bus {
+ samsung,pins = "gpa0-6", "gpa0-7";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart2_data: uart2-data {
+ samsung,pins = "gpa1-0", "gpa1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart2_fctl: uart2-fctl {
+ samsung,pins = "gpa1-2", "gpa1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c3_bus: i2c3-bus {
+ samsung,pins = "gpa1-2", "gpa1-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart3_data: uart3-data {
+ samsung,pins = "gpa1-4", "gpa1-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi0_bus: spi0-bus {
+ samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi1_bus: spi1-bus {
+ samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c4_hs_bus: i2c4-hs-bus {
+ samsung,pins = "gpa2-0", "gpa2-1";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c5_hs_bus: i2c5-hs-bus {
+ samsung,pins = "gpa2-2", "gpa2-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2s1_bus: i2s1-bus {
+ samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
+ "gpb0-4";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ pcm1_bus: pcm1-bus {
+ samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
+ "gpb0-4";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2s2_bus: i2s2-bus {
+ samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3",
+ "gpb1-4";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ pcm2_bus: pcm2-bus {
+ samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3",
+ "gpb1-4";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ spdif_bus: spdif-bus {
+ samsung,pins = "gpb1-0", "gpb1-1";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi2_bus: spi2-bus {
+ samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4";
+ samsung,pin-function = <5>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c6_hs_bus: i2c6-hs-bus {
+ samsung,pins = "gpb1-3", "gpb1-4";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c7_hs_bus: i2c7-hs-bus {
+ samsung,pins = "gpb2-2", "gpb2-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c0_bus: i2c0-bus {
+ samsung,pins = "gpb3-0", "gpb3-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c1_bus: i2c1-bus {
+ samsung,pins = "gpb3-2", "gpb3-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c8_hs_bus: i2c8-hs-bus {
+ samsung,pins = "gpb3-4", "gpb3-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c9_hs_bus: i2c9-hs-bus {
+ samsung,pins = "gpb3-6", "gpb3-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c10_hs_bus: i2c10-hs-bus {
+ samsung,pins = "gpb4-0", "gpb4-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+ };
+
+ pinctrl@03860000 {
+ gpz: gpz {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ i2s0_bus: i2s0-bus {
+ samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+ "gpz-4", "gpz-5", "gpz-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
new file mode 100644
index 0000000000000000000000000000000000000000..08607df6a180904d47b864619a06e48f088bfb8e
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -0,0 +1,33 @@
+/*
+ * SAMSUNG SMDK5420 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5420.dtsi"
+
+/ {
+ model = "Samsung SMDK5420 board based on EXYNOS5420";
+ compatible = "samsung,smdk5420", "samsung,exynos5420";
+
+ memory {
+ reg = <0x20000000 0x80000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200 init=/linuxrc";
+ };
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = "samsung,exynos5420-oscclk";
+ clock-frequency = <24000000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..8c54c4b74f0e5817bbc79dfaf924108a7ea70c0e
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -0,0 +1,148 @@
+/*
+ * SAMSUNG EXYNOS5420 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
+ * EXYNOS5420 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "exynos5.dtsi"
+/include/ "exynos5420-pinctrl.dtsi"
+/ {
+ compatible = "samsung,exynos5420";
+
+ aliases {
+ pinctrl0 = &pinctrl_0;
+ pinctrl1 = &pinctrl_1;
+ pinctrl2 = &pinctrl_2;
+ pinctrl3 = &pinctrl_3;
+ pinctrl4 = &pinctrl_4;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x0>;
+ clock-frequency = <1800000000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x1>;
+ clock-frequency = <1800000000>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x2>;
+ clock-frequency = <1800000000>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x3>;
+ clock-frequency = <1800000000>;
+ };
+ };
+
+ clock: clock-controller@0x10010000 {
+ compatible = "samsung,exynos5420-clock";
+ reg = <0x10010000 0x30000>;
+ #clock-cells = <1>;
+ };
+
+ mct@101C0000 {
+ compatible = "samsung,exynos4210-mct";
+ reg = <0x101C0000 0x800>;
+ interrupt-controller;
+ #interrups-cells = <1>;
+ interrupt-parent = <&mct_map>;
+ interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
+ clocks = <&clock 1>, <&clock 315>;
+ clock-names = "fin_pll", "mct";
+
+ mct_map: mct-map {
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = <0 &combiner 23 3>,
+ <1 &combiner 23 4>,
+ <2 &combiner 25 2>,
+ <3 &combiner 25 3>,
+ <4 &gic 0 120 0>,
+ <5 &gic 0 121 0>,
+ <6 &gic 0 122 0>,
+ <7 &gic 0 123 0>;
+ };
+ };
+
+ pinctrl_0: pinctrl@13400000 {
+ compatible = "samsung,exynos5420-pinctrl";
+ reg = <0x13400000 0x1000>;
+ interrupts = <0 45 0>;
+
+ wakeup-interrupt-controller {
+ compatible = "samsung,exynos4210-wakeup-eint";
+ interrupt-parent = <&gic>;
+ interrupts = <0 32 0>;
+ };
+ };
+
+ pinctrl_1: pinctrl@13410000 {
+ compatible = "samsung,exynos5420-pinctrl";
+ reg = <0x13410000 0x1000>;
+ interrupts = <0 78 0>;
+ };
+
+ pinctrl_2: pinctrl@14000000 {
+ compatible = "samsung,exynos5420-pinctrl";
+ reg = <0x14000000 0x1000>;
+ interrupts = <0 46 0>;
+ };
+
+ pinctrl_3: pinctrl@14010000 {
+ compatible = "samsung,exynos5420-pinctrl";
+ reg = <0x14010000 0x1000>;
+ interrupts = <0 50 0>;
+ };
+
+ pinctrl_4: pinctrl@03860000 {
+ compatible = "samsung,exynos5420-pinctrl";
+ reg = <0x03860000 0x1000>;
+ interrupts = <0 47 0>;
+ };
+
+ serial@12C00000 {
+ clocks = <&clock 257>, <&clock 128>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ serial@12C10000 {
+ clocks = <&clock 258>, <&clock 129>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ serial@12C20000 {
+ clocks = <&clock 259>, <&clock 130>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ serial@12C30000 {
+ clocks = <&clock 260>, <&clock 131>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+};
diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..9565199bce7a0986e3641d0c5e421a6cfefef12c
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-classic.dtsi
@@ -0,0 +1,74 @@
+/*
+ * linux/arch/arm/boot/nspire-classic.dts
+ *
+ * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/include/ "nspire.dtsi"
+
+&lcd {
+ lcd-type = "classic";
+};
+
+&fast_timer {
+ /* compatible = "lsi,zevio-timer"; */
+ reg = <0x90010000 0x1000>, <0x900A0010 0x8>;
+};
+
+&uart {
+ compatible = "ns16550";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb_pclk>;
+ no-loopback-test;
+};
+
+&timer0 {
+ /* compatible = "lsi,zevio-timer"; */
+ reg = <0x900C0000 0x1000>, <0x900A0018 0x8>;
+};
+
+&timer1 {
+ compatible = "lsi,zevio-timer";
+ reg = <0x900D0000 0x1000>, <0x900A0020 0x8>;
+};
+
+&keypad {
+ active-low;
+
+};
+
+&base_clk {
+ compatible = "lsi,nspire-classic-clock";
+};
+
+&ahb_clk {
+ compatible = "lsi,nspire-classic-ahb-divider";
+};
+
+/ {
+ memory {
+ device_type = "memory";
+ reg = <0x10000000 0x2000000>; /* 32 MB */
+ };
+
+ ahb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ intc: interrupt-controller@DC000000 {
+ compatible = "lsi,zevio-intc";
+ interrupt-controller;
+ reg = <0xDC000000 0x1000>;
+ #interrupt-cells = <1>;
+ };
+ };
+ chosen {
+ bootargs = "debug earlyprintk console=tty0 console=ttyS0,115200n8 root=/dev/ram0";
+ };
+};
diff --git a/arch/arm/boot/dts/nspire-clp.dts b/arch/arm/boot/dts/nspire-clp.dts
new file mode 100644
index 0000000000000000000000000000000000000000..fa5a044656dedeb1550fc6efb03a251180d2cb92
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-clp.dts
@@ -0,0 +1,45 @@
+/*
+ * linux/arch/arm/boot/nspire-clp.dts
+ *
+ * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+
+/include/ "nspire-classic.dtsi"
+
+&keypad {
+ linux,keymap = <
+ 0x0000001c 0x0001001c 0x00020039
+ 0x0004002c 0x00050034 0x00060015
+ 0x0007000b 0x0008002d 0x01000033
+ 0x0101004e 0x01020011 0x01030004
+ 0x0104002f 0x01050003 0x01060016
+ 0x01070002 0x01080014 0x02000062
+ 0x0201000c 0x0202001f 0x02030007
+ 0x02040013 0x02050006 0x02060010
+ 0x02070005 0x02080019 0x03000027
+ 0x03010037 0x03020018 0x0303000a
+ 0x03040031 0x03050009 0x03060032
+ 0x03070008 0x03080026 0x04000028
+ 0x04010035 0x04020025 0x04040024
+ 0x04060017 0x04080023 0x05000028
+ 0x05020022 0x0503001b 0x05040021
+ 0x0505001a 0x05060012 0x0507006f
+ 0x05080020 0x0509002a 0x0601001c
+ 0x0602002e 0x06030068 0x06040030
+ 0x0605006d 0x0606001e 0x06070001
+ 0x0608002b 0x0609000f 0x07000067
+ 0x0702006a 0x0704006c 0x07060069
+ 0x0707000e 0x0708001d 0x070a000d
+ >;
+};
+
+/ {
+ model = "TI-NSPIRE Clickpad";
+ compatible = "ti,nspire-clp";
+};
diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts
new file mode 100644
index 0000000000000000000000000000000000000000..375b924f60d80326833c13e7fbfa5f54c87d37aa
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-cx.dts
@@ -0,0 +1,112 @@
+/*
+ * linux/arch/arm/boot/nspire-cx.dts
+ *
+ * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+
+/include/ "nspire.dtsi"
+
+&lcd {
+ lcd-type = "cx";
+};
+
+&fast_timer {
+ /* compatible = "arm,sp804", "arm,primecell"; */
+};
+
+&uart {
+ compatible = "arm,pl011", "arm,primecell";
+
+ clocks = <&uart_clk>, <&apb_pclk>;
+ clock-names = "uart_clk", "apb_pclk";
+};
+
+&timer0 {
+ compatible = "arm,sp804", "arm,primecell";
+};
+
+&timer1 {
+ compatible = "arm,sp804", "arm,primecell";
+};
+
+&base_clk {
+ compatible = "lsi,nspire-cx-clock";
+};
+
+&ahb_clk {
+ compatible = "lsi,nspire-cx-ahb-divider";
+};
+
+&keypad {
+ linux,keymap = <
+ 0x0000001c 0x0001001c 0x00040039
+ 0x0005002c 0x00060015 0x0007000b
+ 0x0008000f 0x0100002d 0x01010011
+ 0x0102002f 0x01030004 0x01040016
+ 0x01050014 0x0106001f 0x01070002
+ 0x010a006a 0x02000013 0x02010010
+ 0x02020019 0x02030007 0x02040018
+ 0x02050031 0x02060032 0x02070005
+ 0x02080028 0x0209006c 0x03000026
+ 0x03010025 0x03020024 0x0303000a
+ 0x03040017 0x03050023 0x03060022
+ 0x03070008 0x03080035 0x03090069
+ 0x04000021 0x04010012 0x04020020
+ 0x0404002e 0x04050030 0x0406001e
+ 0x0407000d 0x04080037 0x04090067
+ 0x05010038 0x0502000c 0x0503001b
+ 0x05040034 0x0505001a 0x05060006
+ 0x05080027 0x0509000e 0x050a006f
+ 0x0600002b 0x0602004e 0x06030068
+ 0x06040003 0x0605006d 0x06060009
+ 0x06070001 0x0609000f 0x0708002a
+ 0x0709001d 0x070a0033 >;
+};
+
+/ {
+ model = "TI-NSPIRE CX";
+ compatible = "ti,nspire-cx";
+
+ memory {
+ device_type = "memory";
+ reg = <0x10000000 0x4000000>; /* 64 MB */
+ };
+
+ uart_clk: uart_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ ahb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ intc: interrupt-controller@DC000000 {
+ compatible = "arm,pl190-vic";
+ interrupt-controller;
+ reg = <0xDC000000 0x1000>;
+ #interrupt-cells = <1>;
+ };
+
+ apb@90000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ i2c@90050000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x90050000 0x1000>;
+ interrupts = <20>;
+ };
+ };
+ };
+ chosen {
+ bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0";
+ };
+};
diff --git a/arch/arm/boot/dts/nspire-tp.dts b/arch/arm/boot/dts/nspire-tp.dts
new file mode 100644
index 0000000000000000000000000000000000000000..621391ce6ed639eaa3819365006f5a2b63683e41
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-tp.dts
@@ -0,0 +1,44 @@
+/*
+ * linux/arch/arm/boot/nspire-tp.dts
+ *
+ * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+
+/include/ "nspire-classic.dtsi"
+
+&keypad {
+ linux,keymap = <
+ 0x0000001c 0x0001001c 0x00040039
+ 0x0005002c 0x00060015 0x0007000b
+ 0x0008000f 0x0100002d 0x01010011
+ 0x0102002f 0x01030004 0x01040016
+ 0x01050014 0x0106001f 0x01070002
+ 0x010a006a 0x02000013 0x02010010
+ 0x02020019 0x02030007 0x02040018
+ 0x02050031 0x02060032 0x02070005
+ 0x02080028 0x0209006c 0x03000026
+ 0x03010025 0x03020024 0x0303000a
+ 0x03040017 0x03050023 0x03060022
+ 0x03070008 0x03080035 0x03090069
+ 0x04000021 0x04010012 0x04020020
+ 0x0404002e 0x04050030 0x0406001e
+ 0x0407000d 0x04080037 0x04090067
+ 0x05010038 0x0502000c 0x0503001b
+ 0x05040034 0x0505001a 0x05060006
+ 0x05080027 0x0509000e 0x050a006f
+ 0x0600002b 0x0602004e 0x06030068
+ 0x06040003 0x0605006d 0x06060009
+ 0x06070001 0x0609000f 0x0708002a
+ 0x0709001d 0x070a0033 >;
+};
+
+/ {
+ model = "TI-NSPIRE Touchpad";
+ compatible = "ti,nspire-tp";
+};
diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..a22ffe633b49b36a3f0d49a243ef7e04841f1af2
--- /dev/null
+++ b/arch/arm/boot/dts/nspire.dtsi
@@ -0,0 +1,175 @@
+/*
+ * linux/arch/arm/boot/nspire.dtsi
+ *
+ * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ interrupt-parent = <&intc>;
+
+ cpus {
+ cpu@0 {
+ compatible = "arm,arm926ejs";
+ };
+ };
+
+ bootrom: bootrom@00000000 {
+ reg = <0x00000000 0x80000>;
+ };
+
+ sram: sram@A4000000 {
+ device = "memory";
+ reg = <0xA4000000 0x20000>;
+ };
+
+ timer_clk: timer_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ base_clk: base_clk {
+ #clock-cells = <0>;
+ reg = <0x900B0024 0x4>;
+ };
+
+ ahb_clk: ahb_clk {
+ #clock-cells = <0>;
+ reg = <0x900B0024 0x4>;
+ clocks = <&base_clk>;
+ };
+
+ apb_pclk: apb_pclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <2>;
+ clock-mult = <1>;
+ clocks = <&ahb_clk>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ spi: spi@A9000000 {
+ reg = <0xA9000000 0x1000>;
+ };
+
+ usb0: usb@B0000000 {
+ reg = <0xB0000000 0x1000>;
+ interrupts = <8>;
+ };
+
+ usb1: usb@B4000000 {
+ reg = <0xB4000000 0x1000>;
+ interrupts = <9>;
+ status = "disabled";
+ };
+
+ lcd: lcd@C0000000 {
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0xC0000000 0x1000>;
+ interrupts = <21>;
+
+ clocks = <&apb_pclk>;
+ clock-names = "apb_pclk";
+ };
+
+ adc: adc@C4000000 {
+ reg = <0xC4000000 0x1000>;
+ interrupts = <11>;
+ };
+
+ tdes: crypto@C8010000 {
+ reg = <0xC8010000 0x1000>;
+ };
+
+ sha256: crypto@CC000000 {
+ reg = <0xCC000000 0x1000>;
+ };
+
+ apb@90000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clock-ranges;
+ ranges;
+
+ gpio: gpio@90000000 {
+ reg = <0x90000000 0x1000>;
+ interrupts = <7>;
+ };
+
+ fast_timer: timer@90010000 {
+ reg = <0x90010000 0x1000>;
+ interrupts = <17>;
+ };
+
+ uart: serial@90020000 {
+ reg = <0x90020000 0x1000>;
+ interrupts = <1>;
+ };
+
+ timer0: timer@900C0000 {
+ reg = <0x900C0000 0x1000>;
+
+ clocks = <&timer_clk>;
+ };
+
+ timer1: timer@900D0000 {
+ reg = <0x900D0000 0x1000>;
+ interrupts = <19>;
+
+ clocks = <&timer_clk>;
+ };
+
+ watchdog: watchdog@90060000 {
+ compatible = "arm,amba-primecell";
+ reg = <0x90060000 0x1000>;
+ interrupts = <3>;
+ };
+
+ rtc: rtc@90090000 {
+ reg = <0x90090000 0x1000>;
+ interrupts = <4>;
+ };
+
+ misc: misc@900A0000 {
+ reg = <0x900A0000 0x1000>;
+ };
+
+ pwr: pwr@900B0000 {
+ reg = <0x900B0000 0x1000>;
+ interrupts = <15>;
+ };
+
+ keypad: input@900E0000 {
+ compatible = "ti,nspire-keypad";
+ reg = <0x900E0000 0x1000>;
+ interrupts = <16>;
+
+ scan-interval = <1000>;
+ row-delay = <200>;
+
+ clocks = <&apb_pclk>;
+ };
+
+ contrast: contrast@900F0000 {
+ reg = <0x900F0000 0x1000>;
+ };
+
+ led: led@90110000 {
+ reg = <0x90110000 0x1000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/st-pincfg.h b/arch/arm/boot/dts/st-pincfg.h
new file mode 100644
index 0000000000000000000000000000000000000000..8c45d85ac13edd437c082c8f63966052b67bdab8
--- /dev/null
+++ b/arch/arm/boot/dts/st-pincfg.h
@@ -0,0 +1,71 @@
+#ifndef _ST_PINCFG_H_
+#define _ST_PINCFG_H_
+
+/* Alternate functions */
+#define ALT1 1
+#define ALT2 2
+#define ALT3 3
+#define ALT4 4
+#define ALT5 5
+#define ALT6 6
+#define ALT7 7
+
+/* Output enable */
+#define OE (1 << 27)
+/* Pull Up */
+#define PU (1 << 26)
+/* Open Drain */
+#define OD (1 << 26)
+#define RT (1 << 23)
+#define INVERTCLK (1 << 22)
+#define CLKNOTDATA (1 << 21)
+#define DOUBLE_EDGE (1 << 20)
+#define CLK_A (0 << 18)
+#define CLK_B (1 << 18)
+#define CLK_C (2 << 18)
+#define CLK_D (3 << 18)
+
+/* User-frendly defines for Pin Direction */
+ /* oe = 0, pu = 0, od = 0 */
+#define IN (0)
+ /* oe = 0, pu = 1, od = 0 */
+#define IN_PU (PU)
+ /* oe = 1, pu = 0, od = 0 */
+#define OUT (OE)
+ /* oe = 1, pu = 0, od = 1 */
+#define BIDIR (OE | OD)
+ /* oe = 1, pu = 1, od = 1 */
+#define BIDIR_PU (OE | PU | OD)
+
+/* RETIME_TYPE */
+/*
+ * B Mode
+ * Bypass retime with optional delay parameter
+ */
+#define BYPASS (0)
+/*
+ * R0, R1, R0D, R1D modes
+ * single-edge data non inverted clock, retime data with clk
+ */
+#define SE_NICLK_IO (RT)
+/*
+ * RIV0, RIV1, RIV0D, RIV1D modes
+ * single-edge data inverted clock, retime data with clk
+ */
+#define SE_ICLK_IO (RT | INVERTCLK)
+/*
+ * R0E, R1E, R0ED, R1ED modes
+ * double-edge data, retime data with clk
+ */
+#define DE_IO (RT | DOUBLE_EDGE)
+/*
+ * CIV0, CIV1 modes with inverted clock
+ * Retiming the clk pins will park clock & reduce the noise within the core.
+ */
+#define ICLK (RT | CLKNOTDATA | INVERTCLK)
+/*
+ * CLK0, CLK1 modes with non-inverted clock
+ * Retiming the clk pins will park clock & reduce the noise within the core.
+ */
+#define NICLK (RT | CLKNOTDATA)
+#endif /* _ST_PINCFG_H_ */
diff --git a/arch/arm/boot/dts/stih415-b2000.dts b/arch/arm/boot/dts/stih415-b2000.dts
new file mode 100644
index 0000000000000000000000000000000000000000..d4af53160435f02f7a1fb3b6dd4788893b092ecb
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-b2000.dts
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stih415.dtsi"
+#include "stih41x-b2000.dtsi"
+/ {
+ model = "STiH415 B2000 Board";
+ compatible = "st,stih415", "st,stih415-b2000";
+};
diff --git a/arch/arm/boot/dts/stih415-b2020.dts b/arch/arm/boot/dts/stih415-b2020.dts
new file mode 100644
index 0000000000000000000000000000000000000000..442b019e9a3a40da7f84031bdf5090a155719e7a
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-b2020.dts
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stih415.dtsi"
+#include "stih41x-b2020.dtsi"
+/ {
+ model = "STiH415 B2020 Board";
+ compatible = "st,stih415", "st,stih415-b2020";
+};
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..174c799df741c0f4efdadad72304bc7a3bfafc22
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-clock.dtsi
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/ {
+ clocks {
+ /*
+ * Fixed 30MHz oscillator input to SoC
+ */
+ CLK_SYSIN: CLK_SYSIN {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <30000000>;
+ };
+
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: arm_periph_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <500000000>;
+ };
+
+ /*
+ * Bootloader initialized system infrastructure clock for
+ * serial devices.
+ */
+ CLKS_ICN_REG_0: CLKS_ICN_REG_0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..1d322b24d1e441bebabfd55d93ec9738b067f1ee
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -0,0 +1,268 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "st-pincfg.h"
+/ {
+
+ aliases {
+ gpio0 = &PIO0;
+ gpio1 = &PIO1;
+ gpio2 = &PIO2;
+ gpio3 = &PIO3;
+ gpio4 = &PIO4;
+ gpio5 = &PIO5;
+ gpio6 = &PIO6;
+ gpio7 = &PIO7;
+ gpio8 = &PIO8;
+ gpio9 = &PIO9;
+ gpio10 = &PIO10;
+ gpio11 = &PIO11;
+ gpio12 = &PIO12;
+ gpio13 = &PIO13;
+ gpio14 = &PIO14;
+ gpio15 = &PIO15;
+ gpio16 = &PIO16;
+ gpio17 = &PIO17;
+ gpio18 = &PIO18;
+ gpio19 = &PIO100;
+ gpio20 = &PIO101;
+ gpio21 = &PIO102;
+ gpio22 = &PIO103;
+ gpio23 = &PIO104;
+ gpio24 = &PIO105;
+ gpio25 = &PIO106;
+ gpio26 = &PIO107;
+ };
+
+ soc {
+ pin-controller-sbc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stih415-sbc-pinctrl";
+ st,syscfg = <&syscfg_sbc>;
+ ranges = <0 0xfe610000 0x5000>;
+
+ PIO0: gpio@fe610000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0 0x100>;
+ st,bank-name = "PIO0";
+ };
+ PIO1: gpio@fe611000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ st,bank-name = "PIO1";
+ };
+ PIO2: gpio@fe612000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ st,bank-name = "PIO2";
+ };
+ PIO3: gpio@fe613000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ st,bank-name = "PIO3";
+ };
+ PIO4: gpio@fe614000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ st,bank-name = "PIO4";
+ };
+
+ sbc_serial1 {
+ pinctrl_sbc_serial1:sbc_serial1 {
+ st,pins {
+ tx = <&PIO2 6 ALT3 OUT>;
+ rx = <&PIO2 7 ALT3 IN>;
+ };
+ };
+ };
+ };
+
+ pin-controller-front {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stih415-front-pinctrl";
+ st,syscfg = <&syscfg_front>;
+ ranges = <0 0xfee00000 0x8000>;
+
+ PIO5: gpio@fee00000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0 0x100>;
+ st,bank-name = "PIO5";
+ };
+ PIO6: gpio@fee01000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ st,bank-name = "PIO6";
+ };
+ PIO7: gpio@fee02000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ st,bank-name = "PIO7";
+ };
+ PIO8: gpio@fee03000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ st,bank-name = "PIO8";
+ };
+ PIO9: gpio@fee04000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ st,bank-name = "PIO9";
+ };
+ PIO10: gpio@fee05000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x5000 0x100>;
+ st,bank-name = "PIO10";
+ };
+ PIO11: gpio@fee06000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x6000 0x100>;
+ st,bank-name = "PIO11";
+ };
+ PIO12: gpio@fee07000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x7000 0x100>;
+ st,bank-name = "PIO12";
+ };
+ };
+
+ pin-controller-rear {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stih415-rear-pinctrl";
+ st,syscfg = <&syscfg_rear>;
+ ranges = <0 0xfe820000 0x8000>;
+
+ PIO13: gpio@fe820000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0 0x100>;
+ st,bank-name = "PIO13";
+ };
+ PIO14: gpio@fe821000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ st,bank-name = "PIO14";
+ };
+ PIO15: gpio@fe822000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ st,bank-name = "PIO15";
+ };
+ PIO16: gpio@fe823000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ st,bank-name = "PIO16";
+ };
+ PIO17: gpio@fe824000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ st,bank-name = "PIO17";
+ };
+ PIO18: gpio@fe825000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x5000 0x100>;
+ st,bank-name = "PIO18";
+ };
+
+ serial2 {
+ pinctrl_serial2: serial2-0 {
+ st,pins {
+ tx = <&PIO17 4 ALT2 OUT>;
+ rx = <&PIO17 5 ALT2 IN>;
+ };
+ };
+ };
+ };
+
+ pin-controller-left {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stih415-left-pinctrl";
+ st,syscfg = <&syscfg_left>;
+ ranges = <0 0xfd6b0000 0x3000>;
+
+ PIO100: gpio@fd6b0000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0 0x100>;
+ st,bank-name = "PIO100";
+ };
+ PIO101: gpio@fd6b1000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ st,bank-name = "PIO101";
+ };
+ PIO102: gpio@fd6b2000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ st,bank-name = "PIO102";
+ };
+ };
+
+ pin-controller-right {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stih415-right-pinctrl";
+ st,syscfg = <&syscfg_right>;
+ ranges = <0 0xfd330000 0x5000>;
+
+ PIO103: gpio@fd330000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0 0x100>;
+ st,bank-name = "PIO103";
+ };
+ PIO104: gpio@fd331000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ st,bank-name = "PIO104";
+ };
+ PIO105: gpio@fd332000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ st,bank-name = "PIO105";
+ };
+ PIO106: gpio@fd333000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ st,bank-name = "PIO106";
+ };
+ PIO107: gpio@fd334000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ st,bank-name = "PIO107";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..74ab8ded4b49b0faf3ecdf4729b22d16fd8b27b8
--- /dev/null
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "stih41x.dtsi"
+#include "stih415-clock.dtsi"
+#include "stih415-pinctrl.dtsi"
+/ {
+
+ L2: cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0xfffe2000 0x1000>;
+ arm,data-latency = <3 2 2>;
+ arm,tag-latency = <1 1 1>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+ compatible = "simple-bus";
+
+ syscfg_sbc: sbc-syscfg@fe600000{
+ compatible = "st,stih415-sbc-syscfg", "syscon";
+ reg = <0xfe600000 0xb4>;
+ };
+
+ syscfg_front: front-syscfg@fee10000{
+ compatible = "st,stih415-front-syscfg", "syscon";
+ reg = <0xfee10000 0x194>;
+ };
+
+ syscfg_rear: rear-syscfg@fe830000{
+ compatible = "st,stih415-rear-syscfg", "syscon";
+ reg = <0xfe830000 0x190>;
+ };
+
+ /* MPE syscfgs */
+ syscfg_left: left-syscfg@fd690000{
+ compatible = "st,stih415-left-syscfg", "syscon";
+ reg = <0xfd690000 0x78>;
+ };
+
+ syscfg_right: right-syscfg@fd320000{
+ compatible = "st,stih415-right-syscfg", "syscon";
+ reg = <0xfd320000 0x180>;
+ };
+
+ syscfg_system: system-syscfg@fdde0000 {
+ compatible = "st,stih415-system-syscfg", "syscon";
+ reg = <0xfdde0000 0x15c>;
+ };
+
+ syscfg_lpm: lpm-syscfg@fe4b5100{
+ compatible = "st,stih415-lpm-syscfg", "syscon";
+ reg = <0xfe4b5100 0x08>;
+ };
+
+ serial2: serial@fed32000 {
+ compatible = "st,asc";
+ status = "disabled";
+ reg = <0xfed32000 0x2c>;
+ interrupts = <0 197 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_serial2>;
+ clocks = <&CLKS_ICN_REG_0>;
+ };
+
+ /* SBC comms block ASCs in SASG1 */
+ sbc_serial1: serial@fe531000 {
+ compatible = "st,asc";
+ status = "disabled";
+ reg = <0xfe531000 0x2c>;
+ interrupts = <0 210 0>;
+ clocks = <&CLK_SYSIN>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sbc_serial1>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stih416-b2000.dts b/arch/arm/boot/dts/stih416-b2000.dts
new file mode 100644
index 0000000000000000000000000000000000000000..a5eb6eee10bfec5af14c3aa277bb81ab75939f8d
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-b2000.dts
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stih416.dtsi"
+#include "stih41x-b2000.dtsi"
+
+/ {
+ compatible = "st,stih416", "st,stih416-b2000";
+ model = "STiH416 B2000";
+};
diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts
new file mode 100644
index 0000000000000000000000000000000000000000..276f28da573abe3cb7ea90f6e39a842954328f20
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-b2020.dts
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stih416.dtsi"
+#include "stih41x-b2020.dtsi"
+/ {
+ model = "STiH416 B2020";
+ compatible = "st,stih416", "st,stih416-b2020";
+
+};
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..7026bf1158d83e90a98a41d731bf1351d4b89bff
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics R&D Limited
+ * <stlinux-devel@stlinux.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/ {
+ clocks {
+ /*
+ * Fixed 30MHz oscillator inputs to SoC
+ */
+ CLK_SYSIN: CLK_SYSIN {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <30000000>;
+ clock-output-names = "CLK_SYSIN";
+ };
+
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: arm_periph_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <600000000>;
+ };
+
+ /*
+ * Bootloader initialized system infrastructure clock for
+ * serial devices.
+ */
+ CLK_S_ICN_REG_0: clockgenA0@4 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "CLK_S_ICN_REG_0";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..957b21a71b4b7f24267908afe8aae4279eaa3c48
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -0,0 +1,295 @@
+
+/*
+ * Copyright (C) 2013 STMicroelectronics Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "st-pincfg.h"
+/ {
+
+ aliases {
+ gpio0 = &PIO0;
+ gpio1 = &PIO1;
+ gpio2 = &PIO2;
+ gpio3 = &PIO3;
+ gpio4 = &PIO4;
+ gpio5 = &PIO40;
+ gpio6 = &PIO5;
+ gpio7 = &PIO6;
+ gpio8 = &PIO7;
+ gpio9 = &PIO8;
+ gpio10 = &PIO9;
+ gpio11 = &PIO10;
+ gpio12 = &PIO11;
+ gpio13 = &PIO12;
+ gpio14 = &PIO30;
+ gpio15 = &PIO31;
+ gpio16 = &PIO13;
+ gpio17 = &PIO14;
+ gpio18 = &PIO15;
+ gpio19 = &PIO16;
+ gpio20 = &PIO17;
+ gpio21 = &PIO18;
+ gpio22 = &PIO100;
+ gpio23 = &PIO101;
+ gpio24 = &PIO102;
+ gpio25 = &PIO103;
+ gpio26 = &PIO104;
+ gpio27 = &PIO105;
+ gpio28 = &PIO106;
+ gpio29 = &PIO107;
+ };
+
+ soc {
+ pin-controller-sbc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stih416-sbc-pinctrl";
+ st,syscfg = <&syscfg_sbc>;
+ ranges = <0 0xfe610000 0x6000>;
+
+ PIO0: gpio@fe610000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0 0x100>;
+ st,bank-name = "PIO0";
+ };
+ PIO1: gpio@fe611000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ st,bank-name = "PIO1";
+ };
+ PIO2: gpio@fe612000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ st,bank-name = "PIO2";
+ };
+ PIO3: gpio@fe613000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ st,bank-name = "PIO3";
+ };
+ PIO4: gpio@fe614000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ st,bank-name = "PIO4";
+ };
+ PIO40: gpio@fe615000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x5000 0x100>;
+ st,bank-name = "PIO40";
+ st,retime-pin-mask = <0x7f>;
+ };
+
+ sbc_serial1 {
+ pinctrl_sbc_serial1: sbc_serial1 {
+ st,pins {
+ tx = <&PIO2 6 ALT3 OUT>;
+ rx = <&PIO2 7 ALT3 IN>;
+ };
+ };
+ };
+ };
+
+ pin-controller-front {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stih416-front-pinctrl";
+ st,syscfg = <&syscfg_front>;
+ ranges = <0 0xfee00000 0x10000>;
+
+ PIO5: gpio@fee00000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0 0x100>;
+ st,bank-name = "PIO5";
+ };
+ PIO6: gpio@fee01000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ st,bank-name = "PIO6";
+ };
+ PIO7: gpio@fee02000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ st,bank-name = "PIO7";
+ };
+ PIO8: gpio@fee03000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ st,bank-name = "PIO8";
+ };
+ PIO9: gpio@fee04000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ st,bank-name = "PIO9";
+ };
+ PIO10: gpio@fee05000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x5000 0x100>;
+ st,bank-name = "PIO10";
+ };
+ PIO11: gpio@fee06000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x6000 0x100>;
+ st,bank-name = "PIO11";
+ };
+ PIO12: gpio@fee07000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x7000 0x100>;
+ st,bank-name = "PIO12";
+ };
+ PIO30: gpio@fee08000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x8000 0x100>;
+ st,bank-name = "PIO30";
+ };
+ PIO31: gpio@fee09000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x9000 0x100>;
+ st,bank-name = "PIO31";
+ };
+ };
+
+ pin-controller-rear {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stih416-rear-pinctrl";
+ st,syscfg = <&syscfg_rear>;
+ ranges = <0 0xfe820000 0x6000>;
+
+ PIO13: gpio@fe820000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0 0x100>;
+ st,bank-name = "PIO13";
+ };
+ PIO14: gpio@fe821000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ st,bank-name = "PIO14";
+ };
+ PIO15: gpio@fe822000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ st,bank-name = "PIO15";
+ };
+ PIO16: gpio@fe823000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ st,bank-name = "PIO16";
+ };
+ PIO17: gpio@fe824000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ st,bank-name = "PIO17";
+ };
+ PIO18: gpio@fe825000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x5000 0x100>;
+ st,bank-name = "PIO18";
+ st,retime-pin-mask = <0xf>;
+ };
+
+ serial2 {
+ pinctrl_serial2: serial2-0 {
+ st,pins {
+ tx = <&PIO17 4 ALT2 OUT>;
+ rx = <&PIO17 5 ALT2 IN>;
+ output-enable = <&PIO11 3 ALT2 OUT>;
+ };
+ };
+ };
+ };
+
+ pin-controller-fvdp-fe {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stih416-fvdp-fe-pinctrl";
+ st,syscfg = <&syscfg_fvdp_fe>;
+ ranges = <0 0xfd6b0000 0x3000>;
+
+ PIO100: gpio@fd6b0000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0 0x100>;
+ st,bank-name = "PIO100";
+ };
+ PIO101: gpio@fd6b1000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ st,bank-name = "PIO101";
+ };
+ PIO102: gpio@fd6b2000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ st,bank-name = "PIO102";
+ };
+ };
+
+ pin-controller-fvdp-lite {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stih416-fvdp-lite-pinctrl";
+ st,syscfg = <&syscfg_fvdp_lite>;
+ ranges = <0 0xfd330000 0x5000>;
+
+ PIO103: gpio@fd330000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0 0x100>;
+ st,bank-name = "PIO103";
+ };
+ PIO104: gpio@fd331000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ st,bank-name = "PIO104";
+ };
+ PIO105: gpio@fd332000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ st,bank-name = "PIO105";
+ };
+ PIO106: gpio@fd333000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ st,bank-name = "PIO106";
+ };
+
+ PIO107: gpio@fd334000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ st,bank-name = "PIO107";
+ st,retime-pin-mask = <0xf>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..3cecd9689a4999927d60aeb1f320dafed99d0965
--- /dev/null
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2012 STMicroelectronics Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "stih41x.dtsi"
+#include "stih416-clock.dtsi"
+#include "stih416-pinctrl.dtsi"
+/ {
+ L2: cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0xfffe2000 0x1000>;
+ arm,data-latency = <3 3 3>;
+ arm,tag-latency = <2 2 2>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+ compatible = "simple-bus";
+
+ syscfg_sbc:sbc-syscfg@fe600000{
+ compatible = "st,stih416-sbc-syscfg", "syscon";
+ reg = <0xfe600000 0x1000>;
+ };
+
+ syscfg_front:front-syscfg@fee10000{
+ compatible = "st,stih416-front-syscfg", "syscon";
+ reg = <0xfee10000 0x1000>;
+ };
+
+ syscfg_rear:rear-syscfg@fe830000{
+ compatible = "st,stih416-rear-syscfg", "syscon";
+ reg = <0xfe830000 0x1000>;
+ };
+
+ /* MPE */
+ syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{
+ compatible = "st,stih416-fvdp-fe-syscfg", "syscon";
+ reg = <0xfddf0000 0x1000>;
+ };
+
+ syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{
+ compatible = "st,stih416-fvdp-lite-syscfg", "syscon";
+ reg = <0xfd6a0000 0x1000>;
+ };
+
+ syscfg_cpu:cpu-syscfg@fdde0000{
+ compatible = "st,stih416-cpu-syscfg", "syscon";
+ reg = <0xfdde0000 0x1000>;
+ };
+
+ syscfg_compo:compo-syscfg@fd320000{
+ compatible = "st,stih416-compo-syscfg", "syscon";
+ reg = <0xfd320000 0x1000>;
+ };
+
+ syscfg_transport:transport-syscfg@fd690000{
+ compatible = "st,stih416-transport-syscfg", "syscon";
+ reg = <0xfd690000 0x1000>;
+ };
+
+ syscfg_lpm:lpm-syscfg@fe4b5100{
+ compatible = "st,stih416-lpm-syscfg", "syscon";
+ reg = <0xfe4b5100 0x8>;
+ };
+
+ serial2: serial@fed32000{
+ compatible = "st,asc";
+ status = "disabled";
+ reg = <0xfed32000 0x2c>;
+ interrupts = <0 197 0>;
+ clocks = <&CLK_S_ICN_REG_0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_serial2>;
+ };
+
+ /* SBC_UART1 */
+ sbc_serial1: serial@fe531000 {
+ compatible = "st,asc";
+ status = "disabled";
+ reg = <0xfe531000 0x2c>;
+ interrupts = <0 210 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sbc_serial1>;
+ clocks = <&CLK_SYSIN>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..8e694d2b8f5b9910879404a8e6e64b00c81c11b8
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/ {
+
+ memory{
+ device_type = "memory";
+ reg = <0x60000000 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyAS0,115200";
+ linux,stdout-path = &serial2;
+ };
+
+ aliases {
+ ttyAS0 = &serial2;
+ };
+
+ soc {
+ serial2: serial@fed32000 {
+ status = "okay";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ fp_led {
+ #gpio-cells = <1>;
+ label = "Front Panel LED";
+ gpios = <&PIO105 7>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ };
+};
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..133e18143b1ba0d2c278d98c45d247a963d08491
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/ {
+ memory{
+ device_type = "memory";
+ reg = <0x40000000 0x80000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyAS0,115200";
+ linux,stdout-path = &sbc_serial1;
+ };
+
+ aliases {
+ ttyAS0 = &sbc_serial1;
+ };
+ soc {
+ sbc_serial1: serial@fe531000 {
+ status = "okay";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ red {
+ #gpio-cells = <1>;
+ label = "Front Panel LED";
+ gpios = <&PIO4 1>;
+ linux,default-trigger = "heartbeat";
+ };
+ green {
+ gpios = <&PIO4 7>;
+ default-state = "off";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stih41x.dtsi b/arch/arm/boot/dts/stih41x.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..7321403cab8a2eaf6811bc93c8ee78b181afbe08
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x.dtsi
@@ -0,0 +1,38 @@
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+ cpu@1 {
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+ };
+
+ intc: interrupt-controller@fffe1000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xfffe1000 0x1000>,
+ <0xfffe0100 0x100>;
+ };
+
+ scu@fffe0000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xfffe0000 0x1000>;
+ };
+
+ timer@fffe0200 {
+ interrupt-parent = <&intc>;
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0xfffe0200 0x100>;
+ interrupts = <1 11 0x04>;
+ clocks = <&arm_periph_clk>;
+ };
+};
diff --git a/arch/arm/include/debug/nspire.S b/arch/arm/include/debug/nspire.S
new file mode 100644
index 0000000000000000000000000000000000000000..886fd276fcbcf719a32bae4224da52d8d41bb210
--- /dev/null
+++ b/arch/arm/include/debug/nspire.S
@@ -0,0 +1,28 @@
+/*
+ * linux/arch/arm/include/debug/nspire.S
+ *
+ * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#define NSPIRE_EARLY_UART_PHYS_BASE 0x90020000
+#define NSPIRE_EARLY_UART_VIRT_BASE 0xfee20000
+
+.macro addruart, rp, rv, tmp
+ ldr \rp, =(NSPIRE_EARLY_UART_PHYS_BASE) @ physical base address
+ ldr \rv, =(NSPIRE_EARLY_UART_VIRT_BASE) @ virtual base address
+.endm
+
+
+#ifdef CONFIG_DEBUG_NSPIRE_CX_UART
+#include <asm/hardware/debug-pl01x.S>
+#endif
+
+#ifdef CONFIG_DEBUG_NSPIRE_CLASSIC_UART
+#define UART_SHIFT 2
+#include <asm/hardware/debug-8250.S>
+#endif
diff --git a/arch/arm/include/debug/sti.S b/arch/arm/include/debug/sti.S
new file mode 100644
index 0000000000000000000000000000000000000000..e3aa58ff17761fd7b1f0b909a075783b3917cb7d
--- /dev/null
+++ b/arch/arm/include/debug/sti.S
@@ -0,0 +1,61 @@
+/*
+ * arch/arm/include/debug/sti.S
+ *
+ * Debugging macro include header
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define STIH41X_COMMS_BASE 0xfed00000
+#define STIH41X_ASC2_BASE (STIH41X_COMMS_BASE+0x32000)
+
+#define STIH41X_SBC_LPM_BASE 0xfe400000
+#define STIH41X_SBC_COMMS_BASE (STIH41X_SBC_LPM_BASE + 0x100000)
+#define STIH41X_SBC_ASC1_BASE (STIH41X_SBC_COMMS_BASE + 0x31000)
+
+
+#define VIRT_ADDRESS(x) (x - 0x1000000)
+
+#if IS_ENABLED(CONFIG_STIH41X_DEBUG_ASC2)
+#define DEBUG_LL_UART_BASE STIH41X_ASC2_BASE
+#endif
+
+#if IS_ENABLED(CONFIG_STIH41X_DEBUG_SBC_ASC1)
+#define DEBUG_LL_UART_BASE STIH41X_SBC_ASC1_BASE
+#endif
+
+#ifndef DEBUG_LL_UART_BASE
+#error "DEBUG UART is not Configured"
+#endif
+
+#define ASC_TX_BUF_OFF 0x04
+#define ASC_CTRL_OFF 0x0c
+#define ASC_STA_OFF 0x14
+
+#define ASC_STA_TX_FULL (1<<9)
+#define ASC_STA_TX_EMPTY (1<<1)
+
+
+ .macro addruart, rp, rv, tmp
+ ldr \rp, =DEBUG_LL_UART_BASE @ physical base
+ ldr \rv, =VIRT_ADDRESS(DEBUG_LL_UART_BASE) @ virt base
+ .endm
+
+ .macro senduart,rd,rx
+ strb \rd, [\rx, #ASC_TX_BUF_OFF]
+ .endm
+
+ .macro waituart,rd,rx
+1001: ldr \rd, [\rx, #ASC_STA_OFF]
+ tst \rd, #ASC_STA_TX_FULL
+ bne 1001b
+ .endm
+
+ .macro busyuart,rd,rx
+1001: ldr \rd, [\rx, #ASC_STA_OFF]
+ tst \rd, #ASC_STA_TX_EMPTY
+ beq 1001b
+ .endm
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 0ecd5af20545976eaef6791da4c9ea12ebf3856e..2d503b3684c4a08048795cbd91788824147f6987 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -78,6 +78,16 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5420
+ bool "SAMSUNG EXYNOS5420"
+ default y
+ depends on ARCH_EXYNOS5
+ select PM_GENERIC_DOMAINS if PM
+ select S5P_PM if PM
+ select S5P_SLEEP if PM
+ help
+ Enable EXYNOS5420 SoC support
+
config SOC_EXYNOS5440
bool "SAMSUNG EXYNOS5440"
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 81e6320ca09185e6fdd1acc9505e2ebca56d8638..2c655db4b78eda055973f7b3b9f03651bfaa3bcf 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -53,6 +53,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5420[] = "EXYNOS5420";
static const char name_exynos5440[] = "EXYNOS5440";
static void exynos4_map_io(void);
@@ -85,6 +86,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.map_io = exynos5_map_io,
.init = exynos_init,
.name = name_exynos5250,
+ }, {
+ .idcode = EXYNOS5420_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5420,
}, {
.idcode = EXYNOS5440_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
@@ -289,10 +296,10 @@ void exynos5_restart(char mode, const char *cmd)
u32 val;
void __iomem *addr;
- if (of_machine_is_compatible("samsung,exynos5250")) {
- val = 0x1;
- addr = EXYNOS_SWRESET;
- } else if (of_machine_is_compatible("samsung,exynos5440")) {
+ val = 0x1;
+ addr = EXYNOS_SWRESET;
+
+ if (of_machine_is_compatible("samsung,exynos5440")) {
u32 status;
np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
@@ -303,9 +310,6 @@ void exynos5_restart(char mode, const char *cmd)
val = __raw_readl(addr);
val = (val & 0xffff0000) | (status & 0xffff);
- } else {
- pr_err("%s: cannot support non-DT\n", __func__);
- return;
}
__raw_writel(val, addr);
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index d405762be1836f6cf27e0fe40478cc60b0d2cd6a..5d7ce36be46fca8fead7db16418f21d78a4e284e 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -28,13 +28,12 @@ static void arch_detect_cpu(void)
/*
* product_id is bits 31:12
- * bits 23:20 describe the exynosX family
- *
+ * bits 23:20 describe the exynosX family
+ * bits 27:24 describe the exynosX family in exynos5420
*/
chip_id >>= 20;
- chip_id &= 0xf;
- if (chip_id == 0x5)
+ if ((chip_id & 0x0f) == 0x5 || (chip_id & 0xf0) == 0x50)
uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
else
uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index d5c8afdeaa39c489d6205e26746609eadb91fb49..f874b773ca134e231df3e21d3c5c5f65caac33a9 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -52,6 +52,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
"samsung,exynos5250",
+ "samsung,exynos5420",
"samsung,exynos5440",
NULL
};
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index d9c6d0ab6a0ca62a9f7d8678709d0fa4baf5c4fa..deba1308ff162eddfb76578f3547e96eb16c8120 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -50,6 +50,8 @@ static inline void __iomem *cpu_boot_reg(int cpu)
boot_reg = cpu_boot_reg_base();
if (soc_is_exynos4412())
boot_reg += 4*cpu;
+ else if (soc_is_exynos5420())
+ boot_reg += 4;
return boot_reg;
}
@@ -180,10 +182,14 @@ static void __init exynos_smp_init_cpus(void)
void __iomem *scu_base = scu_base_addr();
unsigned int i, ncores;
- if (soc_is_exynos5250())
- ncores = 2;
- else
+ if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
ncores = scu_base ? scu_get_core_count(scu_base) : 1;
+ else
+ /*
+ * CPU Nodes are passed thru DT and set_cpu_possible
+ * is set by "arm_dt_init_cpu_maps".
+ */
+ return;
/* sanity check */
if (ncores > nr_cpu_ids) {
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 1a26d04c9400d46a7a72266aeb040e0b9e66dd9f..d257ff40e16b4a962f929b3c3067939760b0563c 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,16 +1,18 @@
obj-y += io.o timer.o
obj-y += clock.o
-obj-$(CONFIG_DEBUG_FS) += clock-debug.o
obj-$(CONFIG_MSM_VIC) += irq-vic.o
obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o
-obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o
-obj-$(CONFIG_ARCH_MSM7X30) += dma.o
-obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
+obj-$(CONFIG_ARCH_MSM7X00A) += irq.o
+obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
+obj-$(CONFIG_ARCH_MSM7X00A) += dma.o
+obj-$(CONFIG_ARCH_MSM7X30) += dma.o
+obj-$(CONFIG_ARCH_QSD8X50) += dma.o
+
obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
obj-$(CONFIG_MSM_SMD) += last_radio_log.o
obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 82eaf88d20266381778b3f4e520bce276c47e212..803651ad4f62956e1850447534deafe2c837e0de 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -59,6 +59,7 @@ static struct platform_device smc91x_device = {
};
static struct platform_device *devices[] __initdata = {
+ &msm_clock_7x01a,
&msm_device_gpio_7201,
&msm_device_uart3,
&msm_device_smd,
@@ -91,7 +92,6 @@ static void __init halibut_fixup(struct tag *tags, char **cmdline,
static void __init halibut_map_io(void)
{
msm_map_common_io();
- msm_clock_init(msm_clocks_7x01a, msm_num_clocks_7x01a);
}
static void __init halibut_init_late(void)
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index 520c141acd0379f8dc2d9e740d70df2f860998d0..db3d8c0bc8a4315411c94a205c7f51265ec35d81 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -89,6 +89,7 @@ struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
};
static struct platform_device *devices[] __initdata = {
+ &msm_clock_7x30,
&msm_device_gpio_7x30,
#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
&msm_device_uart2,
@@ -116,7 +117,6 @@ static void __init msm7x30_init(void)
static void __init msm7x30_map_io(void)
{
msm_map_msm7x30_io();
- msm_clock_init(msm_clocks_7x30, msm_num_clocks_7x30);
}
static void __init msm7x30_init_late(void)
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 38a532d6937cc9f5186b62ead4f1b0822ae32e44..f14a73d86bc06e21243c268d87c5adfa230073dc 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -89,6 +89,7 @@ static struct msm_otg_platform_data msm_otg_pdata = {
};
static struct platform_device *devices[] __initdata = {
+ &msm_clock_8x50,
&msm_device_gpio_8x50,
&msm_device_uart3,
&msm_device_smd,
@@ -172,7 +173,6 @@ static void __init qsd8x50_init_mmc(void)
static void __init qsd8x50_map_io(void)
{
msm_map_qsd8x50_io();
- msm_clock_init(msm_clocks_8x50, msm_num_clocks_8x50);
}
static void __init qsd8x50_init_irq(void)
diff --git a/arch/arm/mach-msm/board-trout-panel.c b/arch/arm/mach-msm/board-trout-panel.c
index f9a5db6d2ced5cd7f1fa68f9d31ac03472045050..77b0a26f897fe4e306aa2a40c96b628a48df4fec 100644
--- a/arch/arm/mach-msm/board-trout-panel.c
+++ b/arch/arm/mach-msm/board-trout-panel.c
@@ -7,7 +7,6 @@
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/leds.h>
-#include <linux/clk.h>
#include <linux/err.h>
#include <asm/io.h>
@@ -19,6 +18,7 @@
#include "board-trout.h"
#include "proc_comm.h"
+#include "clock-pcom.h"
#include "devices.h"
#define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255
@@ -170,7 +170,6 @@ static struct mddi_table mddi_toshiba_init_table[] = {
#define INTMASK_VWAKEOUT (1U << 0)
-static struct clk *gp_clk;
static int trout_new_backlight = 1;
static struct vreg *vreg_mddi_1v5;
static struct vreg *vreg_lcm_2v85;
@@ -273,18 +272,14 @@ int __init trout_init_panel(void)
} else {
uint32_t config = PCOM_GPIO_CFG(27, 1, GPIO_OUTPUT,
GPIO_NO_PULL, GPIO_8MA);
+ uint32_t id = P_GP_CLK;
+ uint32_t rate = 19200000;
+
msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
- gp_clk = clk_get(NULL, "gp_clk");
- if (IS_ERR(gp_clk)) {
- printk(KERN_ERR "trout_init_panel: could not get gp"
- "clock\n");
- gp_clk = NULL;
- }
- rc = clk_set_rate(gp_clk, 19200000);
- if (rc)
- printk(KERN_ERR "trout_init_panel: set clock rate "
- "failed\n");
+ msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
+ if (id < 0)
+ pr_err("trout_init_panel: set clock rate failed\n");
}
rc = platform_device_register(&msm_device_mdp);
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 80fe1c5ff5c13413986d35bed3381ef62f2bdf9c..64a46eb4fc494cebf38bbc9a33427e57ff820cba 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -36,6 +36,7 @@
extern int trout_init_mmc(unsigned int);
static struct platform_device *devices[] __initdata = {
+ &msm_clock_7x01a,
&msm_device_gpio_7201,
&msm_device_uart3,
&msm_device_smd,
@@ -94,8 +95,6 @@ static void __init trout_map_io(void)
/* route UART3 to the "H2W" extended usb connector */
writeb(0x80, TROUT_CPLD_BASE + 0x00);
#endif
-
- msm_clock_init(msm_clocks_7x01a, msm_num_clocks_7x01a);
}
static void __init trout_init_late(void)
diff --git a/arch/arm/mach-msm/clock-7x30.h b/arch/arm/mach-msm/clock-7x30.h
deleted file mode 100644
index 14104453688bd3fed7db46f35f183a6140e6376e..0000000000000000000000000000000000000000
--- a/arch/arm/mach-msm/clock-7x30.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
-#define __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
-
-enum {
- L_7X30_NONE_CLK = -1,
- L_7X30_ADM_CLK,
- L_7X30_I2C_CLK,
- L_7X30_I2C_2_CLK,
- L_7X30_QUP_I2C_CLK,
- L_7X30_UART1DM_CLK,
- L_7X30_UART1DM_P_CLK,
- L_7X30_UART2DM_CLK,
- L_7X30_UART2DM_P_CLK,
- L_7X30_EMDH_CLK,
- L_7X30_EMDH_P_CLK,
- L_7X30_PMDH_CLK,
- L_7X30_PMDH_P_CLK,
- L_7X30_GRP_2D_CLK,
- L_7X30_GRP_2D_P_CLK,
- L_7X30_GRP_3D_SRC_CLK,
- L_7X30_GRP_3D_CLK,
- L_7X30_GRP_3D_P_CLK,
- L_7X30_IMEM_CLK,
- L_7X30_SDC1_CLK,
- L_7X30_SDC1_P_CLK,
- L_7X30_SDC2_CLK,
- L_7X30_SDC2_P_CLK,
- L_7X30_SDC3_CLK,
- L_7X30_SDC3_P_CLK,
- L_7X30_SDC4_CLK,
- L_7X30_SDC4_P_CLK,
- L_7X30_MDP_CLK,
- L_7X30_MDP_P_CLK,
- L_7X30_MDP_LCDC_PCLK_CLK,
- L_7X30_MDP_LCDC_PAD_PCLK_CLK,
- L_7X30_MDP_VSYNC_CLK,
- L_7X30_MI2S_CODEC_RX_M_CLK,
- L_7X30_MI2S_CODEC_RX_S_CLK,
- L_7X30_MI2S_CODEC_TX_M_CLK,
- L_7X30_MI2S_CODEC_TX_S_CLK,
- L_7X30_MI2S_M_CLK,
- L_7X30_MI2S_S_CLK,
- L_7X30_LPA_CODEC_CLK,
- L_7X30_LPA_CORE_CLK,
- L_7X30_LPA_P_CLK,
- L_7X30_MIDI_CLK,
- L_7X30_MDC_CLK,
- L_7X30_ROTATOR_IMEM_CLK,
- L_7X30_ROTATOR_P_CLK,
- L_7X30_SDAC_M_CLK,
- L_7X30_SDAC_CLK,
- L_7X30_UART1_CLK,
- L_7X30_UART2_CLK,
- L_7X30_UART3_CLK,
- L_7X30_TV_CLK,
- L_7X30_TV_DAC_CLK,
- L_7X30_TV_ENC_CLK,
- L_7X30_HDMI_CLK,
- L_7X30_TSIF_REF_CLK,
- L_7X30_TSIF_P_CLK,
- L_7X30_USB_HS_SRC_CLK,
- L_7X30_USB_HS_CLK,
- L_7X30_USB_HS_CORE_CLK,
- L_7X30_USB_HS_P_CLK,
- L_7X30_USB_HS2_CLK,
- L_7X30_USB_HS2_CORE_CLK,
- L_7X30_USB_HS2_P_CLK,
- L_7X30_USB_HS3_CLK,
- L_7X30_USB_HS3_CORE_CLK,
- L_7X30_USB_HS3_P_CLK,
- L_7X30_VFE_CLK,
- L_7X30_VFE_P_CLK,
- L_7X30_VFE_MDC_CLK,
- L_7X30_VFE_CAMIF_CLK,
- L_7X30_CAMIF_PAD_P_CLK,
- L_7X30_CAM_M_CLK,
- L_7X30_JPEG_CLK,
- L_7X30_JPEG_P_CLK,
- L_7X30_VPE_CLK,
- L_7X30_MFC_CLK,
- L_7X30_MFC_DIV2_CLK,
- L_7X30_MFC_P_CLK,
- L_7X30_SPI_CLK,
- L_7X30_SPI_P_CLK,
- L_7X30_CSI0_CLK,
- L_7X30_CSI0_VFE_CLK,
- L_7X30_CSI0_P_CLK,
- L_7X30_CSI1_CLK,
- L_7X30_CSI1_VFE_CLK,
- L_7X30_CSI1_P_CLK,
- L_7X30_GLBL_ROOT_CLK,
-
- L_7X30_AXI_LI_VG_CLK,
- L_7X30_AXI_LI_GRP_CLK,
- L_7X30_AXI_LI_JPEG_CLK,
- L_7X30_AXI_GRP_2D_CLK,
- L_7X30_AXI_MFC_CLK,
- L_7X30_AXI_VPE_CLK,
- L_7X30_AXI_LI_VFE_CLK,
- L_7X30_AXI_LI_APPS_CLK,
- L_7X30_AXI_MDP_CLK,
- L_7X30_AXI_IMEM_CLK,
- L_7X30_AXI_LI_ADSP_A_CLK,
- L_7X30_AXI_ROTATOR_CLK,
-
- L_7X30_NR_CLKS
-};
-
-struct clk_ops;
-extern struct clk_ops clk_ops_7x30;
-
-struct clk_ops *clk_7x30_is_local(uint32_t id);
-int clk_7x30_init(void);
-
-void pll_enable(uint32_t pll);
-void pll_disable(uint32_t pll);
-
-extern int internal_pwr_rail_ctl_auto(unsigned rail_id, bool enable);
-
-#define CLK_7X30(clk_name, clk_id, clk_dev, clk_flags) { \
- .con_id = clk_name, \
- .dev_id = clk_dev, \
- .clk = &(struct clk){ \
- .id = L_7X30_##clk_id, \
- .remote_id = P_##clk_id, \
- .flags = clk_flags, \
- .dbg_name = #clk_id, \
- }, \
- }
-
-#define CLK_7X30S(clk_name, l_id, r_id, clk_dev, clk_flags) { \
- .con_id = clk_name, \
- .dev_id = clk_dev, \
- .clk = &(struct clk){ \
- .id = L_7X30_##l_id, \
- .remote_id = P_##r_id, \
- .flags = clk_flags, \
- .dbg_name = #l_id, \
- .ops = &clk_ops_pcom, \
- }, \
- }
-
-#endif
diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c
deleted file mode 100644
index b0fbdf1cbdd15040709940826fe013b4c637b51d..0000000000000000000000000000000000000000
--- a/arch/arm/mach-msm/clock-debug.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/ctype.h>
-#include <linux/debugfs.h>
-#include <linux/clk.h>
-#include "clock.h"
-
-static int clock_debug_rate_set(void *data, u64 val)
-{
- struct clk *clock = data;
- int ret;
-
- /* Only increases to max rate will succeed, but that's actually good
- * for debugging purposes so we don't check for error. */
- if (clock->flags & CLK_MAX)
- clk_set_max_rate(clock, val);
- if (clock->flags & CLK_MIN)
- ret = clk_set_min_rate(clock, val);
- else
- ret = clk_set_rate(clock, val);
- if (ret != 0)
- printk(KERN_ERR "clk_set%s_rate failed (%d)\n",
- (clock->flags & CLK_MIN) ? "_min" : "", ret);
- return ret;
-}
-
-static int clock_debug_rate_get(void *data, u64 *val)
-{
- struct clk *clock = data;
- *val = clk_get_rate(clock);
- return 0;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_debug_rate_get,
- clock_debug_rate_set, "%llu\n");
-
-static int clock_debug_enable_set(void *data, u64 val)
-{
- struct clk *clock = data;
- int rc = 0;
-
- if (val)
- rc = clock->ops->enable(clock->id);
- else
- clock->ops->disable(clock->id);
-
- return rc;
-}
-
-static int clock_debug_enable_get(void *data, u64 *val)
-{
- struct clk *clock = data;
-
- *val = clock->ops->is_enabled(clock->id);
-
- return 0;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(clock_enable_fops, clock_debug_enable_get,
- clock_debug_enable_set, "%llu\n");
-
-static int clock_debug_local_get(void *data, u64 *val)
-{
- struct clk *clock = data;
-
- *val = clock->ops->is_local(clock->id);
-
- return 0;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(clock_local_fops, clock_debug_local_get,
- NULL, "%llu\n");
-
-static struct dentry *debugfs_base;
-
-int __init clock_debug_init(void)
-{
- debugfs_base = debugfs_create_dir("clk", NULL);
- if (!debugfs_base)
- return -ENOMEM;
- return 0;
-}
-
-int __init clock_debug_add(struct clk *clock)
-{
- char temp[50], *ptr;
- struct dentry *clk_dir;
-
- if (!debugfs_base)
- return -ENOMEM;
-
- strlcpy(temp, clock->dbg_name, ARRAY_SIZE(temp));
- for (ptr = temp; *ptr; ptr++)
- *ptr = tolower(*ptr);
-
- clk_dir = debugfs_create_dir(temp, debugfs_base);
- if (!clk_dir)
- return -ENOMEM;
-
- if (!debugfs_create_file("rate", S_IRUGO | S_IWUSR, clk_dir,
- clock, &clock_rate_fops))
- goto error;
-
- if (!debugfs_create_file("enable", S_IRUGO | S_IWUSR, clk_dir,
- clock, &clock_enable_fops))
- goto error;
-
- if (!debugfs_create_file("is_local", S_IRUGO, clk_dir, clock,
- &clock_local_fops))
- goto error;
- return 0;
-error:
- debugfs_remove_recursive(clk_dir);
- return -ENOMEM;
-}
diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c
index a52c970df1574a2a0807a183c6bdff2195b40a28..9a80449518e6fdd5393b63a4af6072e1e8d323b9 100644
--- a/arch/arm/mach-msm/clock-pcom.c
+++ b/arch/arm/mach-msm/clock-pcom.c
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -13,20 +13,33 @@
*
*/
+#include <linux/kernel.h>
#include <linux/err.h>
-#include <linux/ctype.h>
-#include <linux/stddef.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+
#include <mach/clk.h>
#include "proc_comm.h"
#include "clock.h"
#include "clock-pcom.h"
-/*
- * glue for the proc_comm interface
- */
-static int pc_clk_enable(unsigned id)
+struct clk_pcom {
+ unsigned id;
+ unsigned long flags;
+ struct msm_clk msm_clk;
+};
+
+static inline struct clk_pcom *to_clk_pcom(struct clk_hw *hw)
{
+ return container_of(to_msm_clk(hw), struct clk_pcom, msm_clk);
+}
+
+static int pc_clk_enable(struct clk_hw *hw)
+{
+ unsigned id = to_clk_pcom(hw)->id;
int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
if (rc < 0)
return rc;
@@ -34,14 +47,16 @@ static int pc_clk_enable(unsigned id)
return (int)id < 0 ? -EINVAL : 0;
}
-static void pc_clk_disable(unsigned id)
+static void pc_clk_disable(struct clk_hw *hw)
{
+ unsigned id = to_clk_pcom(hw)->id;
msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
}
-int pc_clk_reset(unsigned id, enum clk_reset_action action)
+static int pc_clk_reset(struct clk_hw *hw, enum clk_reset_action action)
{
int rc;
+ unsigned id = to_clk_pcom(hw)->id;
if (action == CLK_RESET_ASSERT)
rc = msm_proc_comm(PCOM_CLKCTL_RPC_RESET_ASSERT, &id, NULL);
@@ -54,85 +69,109 @@ int pc_clk_reset(unsigned id, enum clk_reset_action action)
return (int)id < 0 ? -EINVAL : 0;
}
-static int pc_clk_set_rate(unsigned id, unsigned rate)
+static int pc_clk_set_rate(struct clk_hw *hw, unsigned long new_rate,
+ unsigned long p_rate)
{
- /* The rate _might_ be rounded off to the nearest KHz value by the
+ struct clk_pcom *p = to_clk_pcom(hw);
+ unsigned id = p->id, rate = new_rate;
+ int rc;
+
+ /*
+ * The rate _might_ be rounded off to the nearest KHz value by the
* remote function. So a return value of 0 doesn't necessarily mean
* that the exact rate was set successfully.
*/
- int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
- if (rc < 0)
- return rc;
- else
- return (int)id < 0 ? -EINVAL : 0;
-}
-
-static int pc_clk_set_min_rate(unsigned id, unsigned rate)
-{
- int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
- if (rc < 0)
- return rc;
- else
- return (int)id < 0 ? -EINVAL : 0;
-}
-
-static int pc_clk_set_max_rate(unsigned id, unsigned rate)
-{
- int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate);
- if (rc < 0)
- return rc;
+ if (p->flags & CLKFLAG_MIN)
+ rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
else
- return (int)id < 0 ? -EINVAL : 0;
-}
-
-static int pc_clk_set_flags(unsigned id, unsigned flags)
-{
- int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags);
+ rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
if (rc < 0)
return rc;
else
return (int)id < 0 ? -EINVAL : 0;
}
-static unsigned pc_clk_get_rate(unsigned id)
+static unsigned long pc_clk_recalc_rate(struct clk_hw *hw, unsigned long p_rate)
{
+ unsigned id = to_clk_pcom(hw)->id;
if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
return 0;
else
return id;
}
-static unsigned pc_clk_is_enabled(unsigned id)
+static int pc_clk_is_enabled(struct clk_hw *hw)
{
+ unsigned id = to_clk_pcom(hw)->id;
if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
return 0;
else
return id;
}
-static long pc_clk_round_rate(unsigned id, unsigned rate)
+static long pc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *p_rate)
{
-
/* Not really supported; pc_clk_set_rate() does rounding on it's own. */
return rate;
}
-static bool pc_clk_is_local(unsigned id)
-{
- return false;
-}
-
-struct clk_ops clk_ops_pcom = {
+static struct clk_ops clk_ops_pcom = {
.enable = pc_clk_enable,
.disable = pc_clk_disable,
- .auto_off = pc_clk_disable,
- .reset = pc_clk_reset,
.set_rate = pc_clk_set_rate,
- .set_min_rate = pc_clk_set_min_rate,
- .set_max_rate = pc_clk_set_max_rate,
- .set_flags = pc_clk_set_flags,
- .get_rate = pc_clk_get_rate,
+ .recalc_rate = pc_clk_recalc_rate,
.is_enabled = pc_clk_is_enabled,
.round_rate = pc_clk_round_rate,
- .is_local = pc_clk_is_local,
};
+
+static int msm_clock_pcom_probe(struct platform_device *pdev)
+{
+ const struct pcom_clk_pdata *pdata = pdev->dev.platform_data;
+ int i, ret;
+
+ for (i = 0; i < pdata->num_lookups; i++) {
+ const struct clk_pcom_desc *desc = &pdata->lookup[i];
+ struct clk *c;
+ struct clk_pcom *p;
+ struct clk_hw *hw;
+ struct clk_init_data init;
+
+ p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
+ if (!p)
+ return -ENOMEM;
+
+ p->id = desc->id;
+ p->flags = desc->flags;
+ p->msm_clk.reset = pc_clk_reset;
+
+ hw = &p->msm_clk.hw;
+ hw->init = &init;
+
+ init.name = desc->name;
+ init.ops = &clk_ops_pcom;
+ init.num_parents = 0;
+ init.flags = CLK_IS_ROOT;
+
+ if (!(p->flags & CLKFLAG_AUTO_OFF))
+ init.flags |= CLK_IGNORE_UNUSED;
+
+ c = devm_clk_register(&pdev->dev, hw);
+ ret = clk_register_clkdev(c, desc->con, desc->dev);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static struct platform_driver msm_clock_pcom_driver = {
+ .probe = msm_clock_pcom_probe,
+ .driver = {
+ .name = "msm-clock-pcom",
+ .owner = THIS_MODULE,
+ },
+};
+module_platform_driver(msm_clock_pcom_driver);
+
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-msm/clock-pcom.h b/arch/arm/mach-msm/clock-pcom.h
index 974d0032f3a3632d736ded9ef168b431d8491001..5bb164fd46a87d1cea7d31a0bc3dfd14b73cccfc 100644
--- a/arch/arm/mach-msm/clock-pcom.h
+++ b/arch/arm/mach-msm/clock-pcom.h
@@ -1,4 +1,5 @@
-/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+/*
+ * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -120,21 +121,25 @@
#define P_NR_CLKS 102
-struct clk_ops;
-extern struct clk_ops clk_ops_pcom;
+struct clk_pcom_desc {
+ unsigned id;
+ const char *name;
+ const char *con;
+ const char *dev;
+ unsigned long flags;
+};
-int pc_clk_reset(unsigned id, enum clk_reset_action action);
+struct pcom_clk_pdata {
+ struct clk_pcom_desc *lookup;
+ u32 num_lookups;
+};
#define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) { \
- .con_id = clk_name, \
- .dev_id = clk_dev, \
- .clk = &(struct clk){ \
- .id = P_##clk_id, \
- .remote_id = P_##clk_id, \
- .ops = &clk_ops_pcom, \
- .flags = clk_flags, \
- .dbg_name = #clk_id, \
- }, \
+ .id = P_##clk_id, \
+ .name = #clk_id, \
+ .con = clk_name, \
+ .dev = clk_dev, \
+ .flags = clk_flags, \
}
#endif
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index d9145dfc2a3b04c4096c1dd10f4ac97ef9ac815f..35ea02b52483771366b89ad5e01c4e98bbde17e5 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -1,7 +1,7 @@
/* arch/arm/mach-msm/clock.c
*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -14,171 +14,15 @@
*
*/
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/err.h>
-#include <linux/spinlock.h>
-#include <linux/pm_qos.h>
-#include <linux/mutex.h>
-#include <linux/clk.h>
-#include <linux/string.h>
+#include <linux/clk-provider.h>
#include <linux/module.h>
-#include <linux/clkdev.h>
#include "clock.h"
-static DEFINE_MUTEX(clocks_mutex);
-static DEFINE_SPINLOCK(clocks_lock);
-static LIST_HEAD(clocks);
-
-/*
- * Standard clock functions defined in include/linux/clk.h
- */
-int clk_enable(struct clk *clk)
-{
- unsigned long flags;
- spin_lock_irqsave(&clocks_lock, flags);
- clk->count++;
- if (clk->count == 1)
- clk->ops->enable(clk->id);
- spin_unlock_irqrestore(&clocks_lock, flags);
- return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
- unsigned long flags;
- spin_lock_irqsave(&clocks_lock, flags);
- BUG_ON(clk->count == 0);
- clk->count--;
- if (clk->count == 0)
- clk->ops->disable(clk->id);
- spin_unlock_irqrestore(&clocks_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
int clk_reset(struct clk *clk, enum clk_reset_action action)
{
- return clk->ops->reset(clk->remote_id, action);
+ struct clk_hw *hw = __clk_get_hw(clk);
+ struct msm_clk *m = to_msm_clk(hw);
+ return m->reset(hw, action);
}
EXPORT_SYMBOL(clk_reset);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- return clk->ops->get_rate(clk->id);
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret;
- if (clk->flags & CLKFLAG_MAX) {
- ret = clk->ops->set_max_rate(clk->id, rate);
- if (ret)
- return ret;
- }
- if (clk->flags & CLKFLAG_MIN) {
- ret = clk->ops->set_min_rate(clk->id, rate);
- if (ret)
- return ret;
- }
-
- if (clk->flags & CLKFLAG_MAX || clk->flags & CLKFLAG_MIN)
- return ret;
-
- return clk->ops->set_rate(clk->id, rate);
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
- return clk->ops->round_rate(clk->id, rate);
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_min_rate(struct clk *clk, unsigned long rate)
-{
- return clk->ops->set_min_rate(clk->id, rate);
-}
-EXPORT_SYMBOL(clk_set_min_rate);
-
-int clk_set_max_rate(struct clk *clk, unsigned long rate)
-{
- return clk->ops->set_max_rate(clk->id, rate);
-}
-EXPORT_SYMBOL(clk_set_max_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
- return -ENOSYS;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-struct clk *clk_get_parent(struct clk *clk)
-{
- return ERR_PTR(-ENOSYS);
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-int clk_set_flags(struct clk *clk, unsigned long flags)
-{
- if (clk == NULL || IS_ERR(clk))
- return -EINVAL;
- return clk->ops->set_flags(clk->id, flags);
-}
-EXPORT_SYMBOL(clk_set_flags);
-
-/* EBI1 is the only shared clock that several clients want to vote on as of
- * this commit. If this changes in the future, then it might be better to
- * make clk_min_rate handle the voting or make ebi1_clk_set_min_rate more
- * generic to support different clocks.
- */
-static struct clk *ebi1_clk;
-
-void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks)
-{
- unsigned n;
-
- mutex_lock(&clocks_mutex);
- for (n = 0; n < num_clocks; n++) {
- clkdev_add(&clock_tbl[n]);
- list_add_tail(&clock_tbl[n].clk->list, &clocks);
- }
- mutex_unlock(&clocks_mutex);
-
- ebi1_clk = clk_get(NULL, "ebi1_clk");
- BUG_ON(ebi1_clk == NULL);
-
-}
-
-/* The bootloader and/or AMSS may have left various clocks enabled.
- * Disable any clocks that belong to us (CLKFLAG_AUTO_OFF) but have
- * not been explicitly enabled by a clk_enable() call.
- */
-static int __init clock_late_init(void)
-{
- unsigned long flags;
- struct clk *clk;
- unsigned count = 0;
-
- clock_debug_init();
- mutex_lock(&clocks_mutex);
- list_for_each_entry(clk, &clocks, list) {
- clock_debug_add(clk);
- if (clk->flags & CLKFLAG_AUTO_OFF) {
- spin_lock_irqsave(&clocks_lock, flags);
- if (!clk->count) {
- count++;
- clk->ops->auto_off(clk->id);
- }
- spin_unlock_irqrestore(&clocks_lock, flags);
- }
- }
- mutex_unlock(&clocks_mutex);
- pr_info("clock_late_init() disabled %d unused clocks\n", count);
- return 0;
-}
-
-late_initcall(clock_late_init);
-
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 2c007f606d2921e61d8692bd7a3e288cf08d588b..42d29dd7aafca23be03b074149747f74cbd8a62e 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -1,7 +1,7 @@
/* arch/arm/mach-msm/clock.h
*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -17,56 +17,27 @@
#ifndef __ARCH_ARM_MACH_MSM_CLOCK_H
#define __ARCH_ARM_MACH_MSM_CLOCK_H
-#include <linux/init.h>
-#include <linux/list.h>
+#include <linux/clk-provider.h>
#include <mach/clk.h>
-#define CLKFLAG_INVERT 0x00000001
-#define CLKFLAG_NOINVERT 0x00000002
-#define CLKFLAG_NONEST 0x00000004
-#define CLKFLAG_NORESET 0x00000008
-
#define CLK_FIRST_AVAILABLE_FLAG 0x00000100
#define CLKFLAG_AUTO_OFF 0x00000200
#define CLKFLAG_MIN 0x00000400
#define CLKFLAG_MAX 0x00000800
-struct clk_ops {
- int (*enable)(unsigned id);
- void (*disable)(unsigned id);
- void (*auto_off)(unsigned id);
- int (*reset)(unsigned id, enum clk_reset_action action);
- int (*set_rate)(unsigned id, unsigned rate);
- int (*set_min_rate)(unsigned id, unsigned rate);
- int (*set_max_rate)(unsigned id, unsigned rate);
- int (*set_flags)(unsigned id, unsigned flags);
- unsigned (*get_rate)(unsigned id);
- unsigned (*is_enabled)(unsigned id);
- long (*round_rate)(unsigned id, unsigned rate);
- bool (*is_local)(unsigned id);
-};
-
-struct clk {
- uint32_t id;
- uint32_t remote_id;
- uint32_t count;
- uint32_t flags;
- struct clk_ops *ops;
- const char *dbg_name;
- struct list_head list;
-};
-
#define OFF CLKFLAG_AUTO_OFF
#define CLK_MIN CLKFLAG_MIN
#define CLK_MAX CLKFLAG_MAX
#define CLK_MINMAX (CLK_MIN | CLK_MAX)
-#ifdef CONFIG_DEBUG_FS
-int __init clock_debug_init(void);
-int __init clock_debug_add(struct clk *clock);
-#else
-static inline int __init clock_debug_init(void) { return 0; }
-static inline int __init clock_debug_add(struct clk *clock) { return 0; }
-#endif
+struct msm_clk {
+ int (*reset)(struct clk_hw *hw, enum clk_reset_action action);
+ struct clk_hw hw;
+};
+
+static inline struct msm_clk *to_msm_clk(struct clk_hw *hw)
+{
+ return container_of(hw, struct msm_clk, hw);
+}
#endif
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c
index 1a0a2306b115567b1d98cec2bc585cb20cf32860..6d50fb96486345b3e7dceb4275cedaada92591b2 100644
--- a/arch/arm/mach-msm/devices-msm7x00.c
+++ b/arch/arm/mach-msm/devices-msm7x00.c
@@ -425,7 +425,7 @@ struct platform_device msm_device_mdp = {
.resource = resources_mdp,
};
-struct clk_lookup msm_clocks_7x01a[] = {
+static struct clk_pcom_desc msm_clocks_7x01a[] = {
CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0),
CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, 0),
@@ -469,4 +469,12 @@ struct clk_lookup msm_clocks_7x01a[] = {
CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF),
};
-unsigned msm_num_clocks_7x01a = ARRAY_SIZE(msm_clocks_7x01a);
+static struct pcom_clk_pdata msm_clock_7x01a_pdata = {
+ .lookup = msm_clocks_7x01a,
+ .num_lookups = ARRAY_SIZE(msm_clocks_7x01a),
+};
+
+struct platform_device msm_clock_7x01a = {
+ .name = "msm-clock-pcom",
+ .dev.platform_data = &msm_clock_7x01a_pdata,
+};
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 12f482c07740429094c0e370d9c8923e872a0b00..d4db75acff569a7adffca73e1ef55368c49b0e9b 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -28,8 +28,8 @@
#include <asm/mach/flash.h>
+#include "clock.h"
#include "clock-pcom.h"
-#include "clock-7x30.h"
#include <linux/platform_data/mmc-msm_sdcc.h>
@@ -161,7 +161,7 @@ struct platform_device msm_device_hsusb_host = {
},
};
-struct clk_lookup msm_clocks_7x30[] = {
+static struct clk_pcom_desc msm_clocks_7x30[] = {
CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0),
CLK_PCOM("cam_m_clk", CAM_M_CLK, NULL, 0),
@@ -177,7 +177,6 @@ struct clk_lookup msm_clocks_7x30[] = {
CLK_PCOM("grp_2d_pclk", GRP_2D_P_CLK, NULL, 0),
CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0),
CLK_PCOM("grp_pclk", GRP_3D_P_CLK, NULL, 0),
- CLK_7X30S("grp_src_clk", GRP_3D_SRC_CLK, GRP_3D_CLK, NULL, 0),
CLK_PCOM("hdmi_clk", HDMI_CLK, NULL, 0),
CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF),
CLK_PCOM("jpeg_clk", JPEG_CLK, NULL, OFF),
@@ -210,7 +209,6 @@ struct clk_lookup msm_clocks_7x30[] = {
CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
CLK_PCOM("spi_clk", SPI_CLK, NULL, 0),
CLK_PCOM("spi_pclk", SPI_P_CLK, NULL, 0),
- CLK_7X30S("tv_src_clk", TV_CLK, TV_ENC_CLK, NULL, 0),
CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0),
CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0),
CLK_PCOM("uart_clk", UART2_CLK, "msm_serial.1", 0),
@@ -237,5 +235,12 @@ struct clk_lookup msm_clocks_7x30[] = {
CLK_PCOM("csi_vfe_clk", CSI0_VFE_CLK, NULL, 0),
};
-unsigned msm_num_clocks_7x30 = ARRAY_SIZE(msm_clocks_7x30);
+static struct pcom_clk_pdata msm_clock_7x30_pdata = {
+ .lookup = msm_clocks_7x30,
+ .num_lookups = ARRAY_SIZE(msm_clocks_7x30),
+};
+struct platform_device msm_clock_7x30 = {
+ .name = "msm-clock-pcom",
+ .dev.platform_data = &msm_clock_7x30_pdata,
+};
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 2e1b3ec9dfc7c2da5489baac857389b6942efb37..f5518112284b9a67895093a625ec32263706aea0 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -28,6 +28,7 @@
#include <asm/mach/flash.h>
#include <linux/platform_data/mmc-msm_sdcc.h>
+#include "clock.h"
#include "clock-pcom.h"
static struct resource msm_gpio_resources[] = {
@@ -322,7 +323,7 @@ int __init msm_add_sdcc(unsigned int controller,
return platform_device_register(pdev);
}
-struct clk_lookup msm_clocks_8x50[] = {
+static struct clk_pcom_desc msm_clocks_8x50[] = {
CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
CLK_PCOM("ce_clk", CE_CLK, NULL, 0),
CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN),
@@ -376,5 +377,12 @@ struct clk_lookup msm_clocks_8x50[] = {
CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0),
};
-unsigned msm_num_clocks_8x50 = ARRAY_SIZE(msm_clocks_8x50);
+static struct pcom_clk_pdata msm_clock_8x50_pdata = {
+ .lookup = msm_clocks_8x50,
+ .num_lookups = ARRAY_SIZE(msm_clocks_8x50),
+};
+struct platform_device msm_clock_8x50 = {
+ .name = "msm-clock-pcom",
+ .dev.platform_data = &msm_clock_8x50_pdata,
+};
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index da902cf5116152eac8b130343aa96ec23f3944bf..dccefad9f9b99fddac51f9af999ccc0fd8afe4d5 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -16,10 +16,6 @@
#ifndef __ARCH_ARM_MACH_MSM_DEVICES_H
#define __ARCH_ARM_MACH_MSM_DEVICES_H
-#include <linux/clkdev.h>
-
-#include "clock.h"
-
extern struct platform_device msm_device_gpio_7201;
extern struct platform_device msm_device_gpio_7x30;
extern struct platform_device msm_device_gpio_8x50;
@@ -50,13 +46,8 @@ extern struct platform_device msm_device_mddi0;
extern struct platform_device msm_device_mddi1;
extern struct platform_device msm_device_mdp;
-extern struct clk_lookup msm_clocks_7x01a[];
-extern unsigned msm_num_clocks_7x01a;
-
-extern struct clk_lookup msm_clocks_7x30[];
-extern unsigned msm_num_clocks_7x30;
-
-extern struct clk_lookup msm_clocks_8x50[];
-extern unsigned msm_num_clocks_8x50;
+extern struct platform_device msm_clock_7x01a;
+extern struct platform_device msm_clock_7x30;
+extern struct platform_device msm_clock_8x50;
#endif
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c
index b279fd8a31b13c6937270997ff646a9851c26247..f8f6adfa07c68d42d60ce6fd8948c6e7283b799c 100644
--- a/arch/arm/mach-msm/dma.c
+++ b/arch/arm/mach-msm/dma.c
@@ -284,6 +284,7 @@ static int __init msm_init_datamover(void)
clk = clk_get(NULL, "adm_clk");
if (IS_ERR(clk))
return PTR_ERR(clk);
+ clk_prepare(clk);
msm_dmov_clk = clk;
ret = request_irq(INT_ADM_AARM, msm_datamover_irq_handler, 0, "msmdatamover", NULL);
if (ret)
@@ -291,6 +292,4 @@ static int __init msm_init_datamover(void)
disable_irq(INT_ADM_AARM);
return 0;
}
-
-arch_initcall(msm_init_datamover);
-
+module_init(msm_init_datamover);
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 8cebedb11233b76b74e5a5738202b69378cf1111..c34e246a3e07dab6cae666d4b6f028d2f6840182 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -20,16 +20,11 @@
#include <linux/types.h>
#include <linux/platform_data/mmc-msm_sdcc.h>
-/* platform device data structures */
-
-struct clk_lookup;
-
/* common init routines for use by arch/arm/mach-msm/board-*.c */
void __init msm_add_devices(void);
void __init msm_init_irq(void);
void __init msm_init_gpio(void);
-void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks);
int __init msm_add_sdcc(unsigned int controller,
struct msm_mmc_platform_data *plat,
unsigned int stat_irq, unsigned long stat_irq_flags);
diff --git a/arch/arm/mach-msm/include/mach/clk.h b/arch/arm/mach-msm/include/mach/clk.h
index e8d38428d8130e5d1e73aa9ed13e8652885fe2e9..fd4f4a7a83b3780a4d0dc140cac88879d0865b45 100644
--- a/arch/arm/mach-msm/include/mach/clk.h
+++ b/arch/arm/mach-msm/include/mach/clk.h
@@ -25,16 +25,7 @@ enum clk_reset_action {
struct clk;
-/* Rate is minimum clock rate in Hz */
-int clk_set_min_rate(struct clk *clk, unsigned long rate);
-
-/* Rate is maximum clock rate in Hz */
-int clk_set_max_rate(struct clk *clk, unsigned long rate);
-
/* Assert/Deassert reset to a hardware block associated with a clock */
int clk_reset(struct clk *clk, enum clk_reset_action action);
-/* Set clock-specific configuration parameters */
-int clk_set_flags(struct clk *clk, unsigned long flags);
-
#endif
diff --git a/arch/arm/mach-nspire/Kconfig b/arch/arm/mach-nspire/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..59d8f0a70919a72f875b0a81cd75b388dcf8a5cb
--- /dev/null
+++ b/arch/arm/mach-nspire/Kconfig
@@ -0,0 +1,16 @@
+config ARCH_NSPIRE
+ bool "TI-NSPIRE based"
+ depends on ARCH_MULTI_V4_V5
+ depends on MMU
+ select CPU_ARM926T
+ select COMMON_CLK
+ select GENERIC_CLOCKEVENTS
+ select GENERIC_IRQ_CHIP
+ select SPARSE_IRQ
+ select ARM_AMBA
+ select ARM_VIC
+ select ARM_TIMER_SP804
+ select USE_OF
+ select CLKSRC_OF
+ help
+ This enables support for systems using the TI-NSPIRE CPU
diff --git a/arch/arm/mach-nspire/Makefile b/arch/arm/mach-nspire/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..1bec256eba07be783d3320a00e88eadf9d64f219
--- /dev/null
+++ b/arch/arm/mach-nspire/Makefile
@@ -0,0 +1,2 @@
+obj-y += nspire.o
+obj-y += clcd.o
diff --git a/arch/arm/mach-nspire/Makefile.boot b/arch/arm/mach-nspire/Makefile.boot
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/arch/arm/mach-nspire/clcd.c b/arch/arm/mach-nspire/clcd.c
new file mode 100644
index 0000000000000000000000000000000000000000..abea12617b173e2b34f794c4bdf98b8b5d518c48
--- /dev/null
+++ b/arch/arm/mach-nspire/clcd.c
@@ -0,0 +1,119 @@
+/*
+ * linux/arch/arm/mach-nspire/clcd.c
+ *
+ * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+#include <linux/dma-mapping.h>
+
+static struct clcd_panel nspire_cx_lcd_panel = {
+ .mode = {
+ .name = "Color LCD",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .pixclock = 1,
+ .hsync_len = 6,
+ .vsync_len = 1,
+ .right_margin = 50,
+ .left_margin = 38,
+ .lower_margin = 3,
+ .upper_margin = 17,
+ },
+ .width = 65, /* ~6.50 cm */
+ .height = 49, /* ~4.87 cm */
+ .tim2 = TIM2_IPC,
+ .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
+ .bpp = 16,
+ .caps = CLCD_CAP_565,
+};
+
+static struct clcd_panel nspire_classic_lcd_panel = {
+ .mode = {
+ .name = "Grayscale LCD",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .pixclock = 1,
+ .hsync_len = 6,
+ .vsync_len = 1,
+ .right_margin = 6,
+ .left_margin = 6,
+ },
+ .width = 71, /* 7.11cm */
+ .height = 53, /* 5.33cm */
+ .tim2 = 0x80007d0,
+ .cntl = CNTL_LCDMONO8,
+ .bpp = 8,
+ .grayscale = 1,
+ .caps = CLCD_CAP_5551,
+};
+
+int nspire_clcd_setup(struct clcd_fb *fb)
+{
+ struct clcd_panel *panel;
+ size_t panel_size;
+ const char *type;
+ dma_addr_t dma;
+ int err;
+
+ BUG_ON(!fb->dev->dev.of_node);
+
+ err = of_property_read_string(fb->dev->dev.of_node, "lcd-type", &type);
+ if (err) {
+ pr_err("CLCD: Could not find lcd-type property\n");
+ return err;
+ }
+
+ if (!strcmp(type, "cx")) {
+ panel = &nspire_cx_lcd_panel;
+ } else if (!strcmp(type, "classic")) {
+ panel = &nspire_classic_lcd_panel;
+ } else {
+ pr_err("CLCD: Unknown lcd-type %s\n", type);
+ return -EINVAL;
+ }
+
+ panel_size = ((panel->mode.xres * panel->mode.yres) * panel->bpp) / 8;
+ panel_size = ALIGN(panel_size, PAGE_SIZE);
+
+ fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
+ panel_size, &dma, GFP_KERNEL);
+
+ if (!fb->fb.screen_base) {
+ pr_err("CLCD: unable to map framebuffer\n");
+ return -ENOMEM;
+ }
+
+ fb->fb.fix.smem_start = dma;
+ fb->fb.fix.smem_len = panel_size;
+ fb->panel = panel;
+
+ return 0;
+}
+
+int nspire_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
+{
+ return dma_mmap_writecombine(&fb->dev->dev, vma,
+ fb->fb.screen_base, fb->fb.fix.smem_start,
+ fb->fb.fix.smem_len);
+}
+
+void nspire_clcd_remove(struct clcd_fb *fb)
+{
+ dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
+ fb->fb.screen_base, fb->fb.fix.smem_start);
+}
diff --git a/arch/arm/mach-nspire/clcd.h b/arch/arm/mach-nspire/clcd.h
new file mode 100644
index 0000000000000000000000000000000000000000..8c33d2c1837177294be8454f50be8fde22225e63
--- /dev/null
+++ b/arch/arm/mach-nspire/clcd.h
@@ -0,0 +1,14 @@
+/*
+ * linux/arch/arm/mach-nspire/clcd.h
+ *
+ * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+int nspire_clcd_setup(struct clcd_fb *fb);
+int nspire_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma);
+void nspire_clcd_remove(struct clcd_fb *fb);
diff --git a/arch/arm/mach-nspire/mmio.h b/arch/arm/mach-nspire/mmio.h
new file mode 100644
index 0000000000000000000000000000000000000000..8813471af4cfadb745ebfde6d0518ad63eddfcf7
--- /dev/null
+++ b/arch/arm/mach-nspire/mmio.h
@@ -0,0 +1,20 @@
+/*
+ * linux/arch/arm/mach-nspire/mmio.h
+ *
+ * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#define NSPIRE_MISC_PHYS_BASE 0x900A0000
+#define NSPIRE_MISC_HWRESET 0x08
+
+#define NSPIRE_PWR_PHYS_BASE 0x900B0000
+#define NSPIRE_PWR_VIRT_BASE 0xFEEB0000
+#define NSPIRE_PWR_BUS_DISABLE1 0x18
+#define NSPIRE_PWR_BUS_DISABLE2 0x20
+
+#define NSPIRE_LCD_PHYS_BASE 0xC0000000
diff --git a/arch/arm/mach-nspire/nspire.c b/arch/arm/mach-nspire/nspire.c
new file mode 100644
index 0000000000000000000000000000000000000000..99e26092a9f7d63b5b096e71895a7eebdf915290
--- /dev/null
+++ b/arch/arm/mach-nspire/nspire.c
@@ -0,0 +1,89 @@
+/*
+ * linux/arch/arm/mach-nspire/nspire.c
+ *
+ * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/init.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/arm-vic.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+#include <linux/clocksource.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+
+#include <asm/hardware/timer-sp.h>
+
+#include "mmio.h"
+#include "clcd.h"
+
+static const char *nspire_dt_match[] __initconst = {
+ "ti,nspire",
+ "ti,nspire-cx",
+ "ti,nspire-tp",
+ "ti,nspire-clp",
+ NULL,
+};
+
+static void __init nspire_map_io(void)
+{
+ debug_ll_io_init();
+}
+
+static struct clcd_board nspire_clcd_data = {
+ .name = "LCD",
+ .caps = CLCD_CAP_5551 | CLCD_CAP_565,
+ .check = clcdfb_check,
+ .decode = clcdfb_decode,
+ .setup = nspire_clcd_setup,
+ .mmap = nspire_clcd_mmap,
+ .remove = nspire_clcd_remove,
+};
+
+
+static struct of_dev_auxdata nspire_auxdata[] __initdata = {
+ OF_DEV_AUXDATA("arm,pl111", NSPIRE_LCD_PHYS_BASE,
+ NULL, &nspire_clcd_data),
+ { }
+};
+
+static void __init nspire_init(void)
+{
+ of_platform_populate(NULL, of_default_bus_match_table,
+ nspire_auxdata, NULL);
+}
+
+static void __init nspire_init_time(void)
+{
+ of_clk_init(NULL);
+ clocksource_of_init();
+}
+
+static void nspire_restart(char mode, const char *cmd)
+{
+ void __iomem *base = ioremap(NSPIRE_MISC_PHYS_BASE, SZ_4K);
+ if (!base)
+ return;
+
+ writel(2, base + NSPIRE_MISC_HWRESET);
+}
+
+DT_MACHINE_START(NSPIRE, "TI-NSPIRE")
+ .dt_compat = nspire_dt_match,
+ .map_io = nspire_map_io,
+ .init_time = nspire_init_time,
+ .init_machine = nspire_init,
+ .restart = nspire_restart,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index b461d93431ed4e29a500e41749e6ca3698090f5f..28f94752b8ff0f2e86024d19c0f1471d02f9d1d5 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -30,17 +30,17 @@
#include <mach/r8a7790.h>
#include <asm/mach/arch.h>
-static const struct resource pfc_resources[] = {
+static struct resource pfc_resources[] __initdata = {
DEFINE_RES_MEM(0xe6060000, 0x250),
};
#define R8A7790_GPIO(idx) \
-static struct resource r8a7790_gpio##idx##_resources[] = { \
+static struct resource r8a7790_gpio##idx##_resources[] __initdata = { \
DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \
DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
}; \
\
-static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data = { \
+static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data __initdata = { \
.gpio_base = 32 * (idx), \
.irq_base = 0, \
.number_of_pins = 32, \
@@ -98,12 +98,20 @@ void __init r8a7790_pinmux_init(void)
[index] = { \
SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
.scbrr_algo_id = SCBRR_ALGO_2, \
- .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
+ .scscr = SCSCR_RE | SCSCR_TE, \
}
-enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 };
+#define HSCIF_DATA(index, baseaddr, irq) \
+[index] = { \
+ SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
+ .scbrr_algo_id = SCBRR_ALGO_6, \
+ .scscr = SCSCR_RE | SCSCR_TE, \
+}
+
+enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
+ HSCIF0, HSCIF1 };
-static const struct plat_sci_port scif[] = {
+static struct plat_sci_port scif[] __initdata = {
SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
@@ -112,6 +120,8 @@ static const struct plat_sci_port scif[] = {
SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
+ HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */
+ HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */
};
static inline void r8a7790_register_scif(int idx)
@@ -120,11 +130,11 @@ static inline void r8a7790_register_scif(int idx)
sizeof(struct plat_sci_port));
}
-static struct renesas_irqc_config irqc0_data = {
+static struct renesas_irqc_config irqc0_data __initdata = {
.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
};
-static struct resource irqc0_resources[] = {
+static struct resource irqc0_resources[] __initdata = {
DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
@@ -149,6 +159,8 @@ void __init r8a7790_add_standard_devices(void)
r8a7790_register_scif(SCIFA2);
r8a7790_register_scif(SCIF0);
r8a7790_register_scif(SCIF1);
+ r8a7790_register_scif(HSCIF0);
+ r8a7790_register_scif(HSCIF1);
r8a7790_register_irqc(0);
}
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..d04e3bfe19189082823e4a74c60d1de1de9eed7f
--- /dev/null
+++ b/arch/arm/mach-sti/Kconfig
@@ -0,0 +1,45 @@
+menuconfig ARCH_STI
+ bool "STMicroelectronics Consumer Electronics SOCs with Device Trees" if ARCH_MULTI_V7
+ select GENERIC_CLOCKEVENTS
+ select CLKDEV_LOOKUP
+ select ARM_GIC
+ select ARM_GLOBAL_TIMER
+ select PINCTRL
+ select PINCTRL_ST
+ select MFD_SYSCON
+ select MIGHT_HAVE_CACHE_L2X0
+ select HAVE_SMP
+ select HAVE_ARM_SCU if SMP
+ select ARCH_REQUIRE_GPIOLIB
+ select ARM_ERRATA_720789
+ select ARM_ERRATA_754322
+ select PL310_ERRATA_753970 if CACHE_PL310
+ select PL310_ERRATA_769419 if CACHE_PL310
+ help
+ Include support for STiH41x SOCs like STiH415/416 using the device tree
+ for discovery
+ More information at Documentation/arm/STiH41x and
+ at Documentation/devicetree
+
+
+if ARCH_STI
+
+config SOC_STIH415
+ bool "STiH415 STMicroelectronics Consumer Electronics family"
+ default y
+ help
+ This enables support for STMicroelectronics Digital Consumer
+ Electronics family StiH415 parts, primarily targetted at set-top-box
+ and other digital audio/video applications using Flattned Device
+ Trees.
+
+config SOC_STIH416
+ bool "STiH416 STMicroelectronics Consumer Electronics family"
+ default y
+ help
+ This enables support for STMicroelectronics Digital Consumer
+ Electronics family StiH416 parts, primarily targetted at set-top-box
+ and other digital audio/video applications using Flattened Device
+ Trees.
+
+endif
diff --git a/arch/arm/mach-sti/Makefile b/arch/arm/mach-sti/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..acb330916333039510c562d18de547020b3c2044
--- /dev/null
+++ b/arch/arm/mach-sti/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+obj-$(CONFIG_ARCH_STI) += board-dt.o
diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c
new file mode 100644
index 0000000000000000000000000000000000000000..8fe6f0c464809691c4be22c040ce4d3a3b72c22e
--- /dev/null
+++ b/arch/arm/mach-sti/board-dt.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author(s): Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clocksource.h>
+#include <linux/irq.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
+
+#include "smp.h"
+
+void __init stih41x_l2x0_init(void)
+{
+ u32 way_size = 0x4;
+ u32 aux_ctrl;
+ /* may be this can be encoded in macros like BIT*() */
+ aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
+ (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
+ (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
+ (way_size << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
+
+ l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
+}
+
+static void __init stih41x_timer_init(void)
+{
+ of_clk_init(NULL);
+ clocksource_of_init();
+ stih41x_l2x0_init();
+}
+
+static const char *stih41x_dt_match[] __initdata = {
+ "st,stih415",
+ "st,stih416",
+ NULL
+};
+
+DT_MACHINE_START(STM, "STiH415/416 SoC with Flattened Device Tree")
+ .init_time = stih41x_timer_init,
+ .smp = smp_ops(sti_smp_ops),
+ .dt_compat = stih41x_dt_match,
+MACHINE_END
diff --git a/arch/arm/mach-sti/headsmp.S b/arch/arm/mach-sti/headsmp.S
new file mode 100644
index 0000000000000000000000000000000000000000..78ebc7559f5309e025c3796ff90017293570bc6e
--- /dev/null
+++ b/arch/arm/mach-sti/headsmp.S
@@ -0,0 +1,44 @@
+/*
+ * arch/arm/mach-sti/headsmp.S
+ *
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * http://www.st.com
+ *
+ * Cloned from linux/arch/arm/mach-vexpress/headsmp.S
+ *
+ * Copyright (c) 2003 ARM Limited
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+ __INIT
+
+/*
+ * ST specific entry point for secondary CPUs. This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(sti_secondary_startup)
+ mrc p15, 0, r0, c0, c0, 5
+ and r0, r0, #15
+ adr r4, 1f
+ ldmia r4, {r5, r6}
+ sub r4, r4, r5
+ add r6, r6, r4
+pen: ldr r7, [r6]
+ cmp r7, r0
+ bne pen
+
+ /*
+ * we've been released from the holding pen: secondary_stack
+ * should now contain the SVC stack for this core
+ */
+ b secondary_startup
+
+1: .long .
+ .long pen_release
diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c
new file mode 100644
index 0000000000000000000000000000000000000000..977a863468fcb715079540328da5d9d3041ef48b
--- /dev/null
+++ b/arch/arm/mach-sti/platsmp.c
@@ -0,0 +1,117 @@
+/*
+ * arch/arm/mach-sti/platsmp.c
+ *
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * http://www.st.com
+ *
+ * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
+ *
+ * Copyright (C) 2002 ARM Ltd.
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+
+#include "smp.h"
+
+static void __cpuinit write_pen_release(int val)
+{
+ pen_release = val;
+ smp_wmb();
+ __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+ outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+}
+
+static DEFINE_SPINLOCK(boot_lock);
+
+void __cpuinit sti_secondary_init(unsigned int cpu)
+{
+ trace_hardirqs_off();
+
+ /*
+ * let the primary processor know we're out of the
+ * pen, then head off into the C entry point
+ */
+ write_pen_release(-1);
+
+ /*
+ * Synchronise with the boot thread.
+ */
+ spin_lock(&boot_lock);
+ spin_unlock(&boot_lock);
+}
+
+int __cpuinit sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ unsigned long timeout;
+
+ /*
+ * set synchronisation state between this boot processor
+ * and the secondary one
+ */
+ spin_lock(&boot_lock);
+
+ /*
+ * The secondary processor is waiting to be released from
+ * the holding pen - release it, then wait for it to flag
+ * that it has been released by resetting pen_release.
+ *
+ * Note that "pen_release" is the hardware CPU ID, whereas
+ * "cpu" is Linux's internal ID.
+ */
+ write_pen_release(cpu_logical_map(cpu));
+
+ /*
+ * Send the secondary CPU a soft interrupt, thereby causing
+ * it to jump to the secondary entrypoint.
+ */
+ arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+ timeout = jiffies + (1 * HZ);
+ while (time_before(jiffies, timeout)) {
+ smp_rmb();
+ if (pen_release == -1)
+ break;
+
+ udelay(10);
+ }
+
+ /*
+ * now the secondary core is starting up let it run its
+ * calibrations, then wait for it to finish
+ */
+ spin_unlock(&boot_lock);
+
+ return pen_release != -1 ? -ENOSYS : 0;
+}
+
+void __init sti_smp_prepare_cpus(unsigned int max_cpus)
+{
+ void __iomem *scu_base = NULL;
+ struct device_node *np = of_find_compatible_node(
+ NULL, NULL, "arm,cortex-a9-scu");
+ if (np) {
+ scu_base = of_iomap(np, 0);
+ scu_enable(scu_base);
+ of_node_put(np);
+ }
+}
+
+struct smp_operations __initdata sti_smp_ops = {
+ .smp_prepare_cpus = sti_smp_prepare_cpus,
+ .smp_secondary_init = sti_secondary_init,
+ .smp_boot_secondary = sti_boot_secondary,
+};
diff --git a/arch/arm/mach-sti/smp.h b/arch/arm/mach-sti/smp.h
new file mode 100644
index 0000000000000000000000000000000000000000..1871b72b1a7e6cd4378f468d9955327bcb78fb97
--- /dev/null
+++ b/arch/arm/mach-sti/smp.h
@@ -0,0 +1,17 @@
+/*
+ * arch/arm/mach-sti/smp.h
+ *
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * http://www.st.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_STI_SMP_H
+#define __MACH_STI_SMP_H
+
+extern struct smp_operations sti_smp_ops;
+
+#endif
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index f58615b5c601b4ab9fc5ffcea0ae332d0a65cd3b..82ccf1d98735520ef4727c615398e478fccb8b02 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -42,7 +42,8 @@ static int __init ux500_l2x0_init(void)
if (cpu_is_u8500_family() || cpu_is_ux540_family())
l2x0_base = __io_address(U8500_L2CC_BASE);
else
- ux500_unknown_soc();
+ /* Non-Ux500 platform */
+ return -ENODEV;
/* Unlock before init */
ux500_l2x0_unlock();
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 989fefe18be6b77bee4216be31948f49582a475b..4fb1f03a10d1f718b9f99d1e5309c9732ebc0a1f 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE0000
#define EXYNOS5250_SOC_ID 0x43520000
+#define EXYNOS5420_SOC_ID 0xE5420000
#define EXYNOS5440_SOC_ID 0xE5440000
#define EXYNOS5_SOC_MASK 0xFFFFF000
@@ -67,6 +68,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
@@ -142,6 +144,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
# define soc_is_exynos5250() 0
#endif
+#if defined(CONFIG_SOC_EXYNOS5420)
+# define soc_is_exynos5420() is_samsung_exynos5420()
+#else
+# define soc_is_exynos5420() 0
+#endif
+
#if defined(CONFIG_SOC_EXYNOS5440)
# define soc_is_exynos5440() is_samsung_exynos5440()
#else
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 187681013bdbe03530c05138623b9c5a2a801265..5d4d432cc4acc1086fba972e9140b37a7c47c17b 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,5 +5,6 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
new file mode 100644
index 0000000000000000000000000000000000000000..68a96cbd4936724da2919498cb3821b52724ed3d
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -0,0 +1,762 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Authors: Thomas Abraham <thomas.ab@samsung.com>
+ * Chander Kashyap <k.chander@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5420 SoC.
+*/
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "clk.h"
+#include "clk-pll.h"
+
+#define SRC_CPU 0x200
+#define DIV_CPU0 0x500
+#define DIV_CPU1 0x504
+#define GATE_BUS_CPU 0x700
+#define GATE_SCLK_CPU 0x800
+#define SRC_TOP0 0x10200
+#define SRC_TOP1 0x10204
+#define SRC_TOP2 0x10208
+#define SRC_TOP3 0x1020c
+#define SRC_TOP4 0x10210
+#define SRC_TOP5 0x10214
+#define SRC_TOP6 0x10218
+#define SRC_TOP7 0x1021c
+#define SRC_DISP10 0x1022c
+#define SRC_MAU 0x10240
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define SRC_PERIC1 0x10254
+#define SRC_TOP10 0x10280
+#define SRC_TOP11 0x10284
+#define SRC_TOP12 0x10288
+#define SRC_MASK_DISP10 0x1032c
+#define SRC_MASK_FSYS 0x10340
+#define SRC_MASK_PERIC0 0x10350
+#define SRC_MASK_PERIC1 0x10354
+#define DIV_TOP0 0x10500
+#define DIV_TOP1 0x10504
+#define DIV_TOP2 0x10508
+#define DIV_DISP10 0x1052c
+#define DIV_MAU 0x10544
+#define DIV_FSYS0 0x10548
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define DIV_PERIC1 0x1055c
+#define DIV_PERIC2 0x10560
+#define DIV_PERIC3 0x10564
+#define DIV_PERIC4 0x10568
+#define GATE_BUS_TOP 0x10700
+#define GATE_BUS_FSYS0 0x10740
+#define GATE_BUS_PERIC 0x10750
+#define GATE_BUS_PERIC1 0x10754
+#define GATE_BUS_PERIS0 0x10760
+#define GATE_BUS_PERIS1 0x10764
+#define GATE_IP_GSCL0 0x10910
+#define GATE_IP_GSCL1 0x10920
+#define GATE_IP_MFC 0x1092c
+#define GATE_IP_DISP1 0x10928
+#define GATE_IP_G3D 0x10930
+#define GATE_IP_GEN 0x10934
+#define GATE_IP_MSCL 0x10970
+#define GATE_TOP_SCLK_GSCL 0x10820
+#define GATE_TOP_SCLK_DISP1 0x10828
+#define GATE_TOP_SCLK_MAU 0x1083c
+#define GATE_TOP_SCLK_FSYS 0x10840
+#define GATE_TOP_SCLK_PERIC 0x10850
+#define SRC_CDREX 0x20200
+#define SRC_KFC 0x28200
+#define DIV_KFC0 0x28500
+
+enum exynos5420_clks {
+ none,
+
+ /* core clocks */
+ fin_pll,
+
+ /* gate for special clocks (sclk) */
+ sclk_uart0 = 128, sclk_uart1, sclk_uart2, sclk_uart3, sclk_mmc0,
+ sclk_mmc1, sclk_mmc2, sclk_spi0, sclk_spi1, sclk_spi2, sclk_i2s1,
+ sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel,
+ sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0,
+ sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro,
+ sclk_pwm, sclk_gscl_wa, sclk_gscl_wb,
+
+ /* gate clocks */
+ aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3,
+ i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, spi0, spi1, spi2, keyif, i2s1,
+ i2s2, pcm1, pcm2, pwm, spdif, i2c8, i2c9, i2c10, aclk66_psgen = 300,
+ chipid, sysreg, tzpc0, tzpc1, tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7,
+ tzpc8, tzpc9, hdmi_cec, seckey, mct, wdt, rtc, tmu, tmu_gpu,
+ pclk66_gpio = 330, aclk200_fsys2 = 350, mmc0, mmc1, mmc2, sromc, ufs,
+ aclk200_fsys = 360, tsi, pdma0, pdma1, rtic, usbh20, usbd300, usbd301,
+ aclk400_mscl = 380, mscl0, mscl1, mscl2, smmu_mscl0, smmu_mscl1,
+ smmu_mscl2, aclk333 = 400, mfc, smmu_mfcl, smmu_mfcr,
+ aclk200_disp1 = 410, dsim1, dp1, hdmi, aclk300_disp1 = 420, fimd1,
+ smmu_fimd1, aclk166 = 430, mixer, aclk266 = 440, rotator, mdma1,
+ smmu_rotator, smmu_mdma1, aclk300_jpeg = 450, jpeg, jpeg2, smmu_jpeg,
+ aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0,
+ gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0,
+ aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
+ smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d,
+
+ nr_clks,
+};
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static __initdata unsigned long exynos5420_clk_regs[] = {
+ SRC_CPU,
+ DIV_CPU0,
+ DIV_CPU1,
+ GATE_BUS_CPU,
+ GATE_SCLK_CPU,
+ SRC_TOP0,
+ SRC_TOP1,
+ SRC_TOP2,
+ SRC_TOP3,
+ SRC_TOP4,
+ SRC_TOP5,
+ SRC_TOP6,
+ SRC_TOP7,
+ SRC_DISP10,
+ SRC_MAU,
+ SRC_FSYS,
+ SRC_PERIC0,
+ SRC_PERIC1,
+ SRC_TOP10,
+ SRC_TOP11,
+ SRC_TOP12,
+ SRC_MASK_DISP10,
+ SRC_MASK_FSYS,
+ SRC_MASK_PERIC0,
+ SRC_MASK_PERIC1,
+ DIV_TOP0,
+ DIV_TOP1,
+ DIV_TOP2,
+ DIV_DISP10,
+ DIV_MAU,
+ DIV_FSYS0,
+ DIV_FSYS1,
+ DIV_FSYS2,
+ DIV_PERIC0,
+ DIV_PERIC1,
+ DIV_PERIC2,
+ DIV_PERIC3,
+ DIV_PERIC4,
+ GATE_BUS_TOP,
+ GATE_BUS_FSYS0,
+ GATE_BUS_PERIC,
+ GATE_BUS_PERIC1,
+ GATE_BUS_PERIS0,
+ GATE_BUS_PERIS1,
+ GATE_IP_GSCL0,
+ GATE_IP_GSCL1,
+ GATE_IP_MFC,
+ GATE_IP_DISP1,
+ GATE_IP_G3D,
+ GATE_IP_GEN,
+ GATE_IP_MSCL,
+ GATE_TOP_SCLK_GSCL,
+ GATE_TOP_SCLK_DISP1,
+ GATE_TOP_SCLK_MAU,
+ GATE_TOP_SCLK_FSYS,
+ GATE_TOP_SCLK_PERIC,
+ SRC_CDREX,
+ SRC_KFC,
+ DIV_KFC0,
+};
+
+/* list of all parent clocks */
+PNAME(mspll_cpu_p) = { "sclk_cpll", "sclk_dpll",
+ "sclk_mpll", "sclk_spll" };
+PNAME(cpu_p) = { "mout_apll" , "mout_mspll_cpu" };
+PNAME(kfc_p) = { "mout_kpll" , "mout_mspll_kfc" };
+PNAME(apll_p) = { "fin_pll", "fout_apll", };
+PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
+PNAME(cpll_p) = { "fin_pll", "fout_cpll", };
+PNAME(dpll_p) = { "fin_pll", "fout_dpll", };
+PNAME(epll_p) = { "fin_pll", "fout_epll", };
+PNAME(ipll_p) = { "fin_pll", "fout_ipll", };
+PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
+PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
+PNAME(rpll_p) = { "fin_pll", "fout_rpll", };
+PNAME(spll_p) = { "fin_pll", "fout_spll", };
+PNAME(vpll_p) = { "fin_pll", "fout_vpll", };
+
+PNAME(group1_p) = { "sclk_cpll", "sclk_dpll", "sclk_mpll" };
+PNAME(group2_p) = { "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll",
+ "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
+PNAME(group3_p) = { "sclk_rpll", "sclk_spll" };
+PNAME(group4_p) = { "sclk_ipll", "sclk_dpll", "sclk_mpll" };
+PNAME(group5_p) = { "sclk_vpll", "sclk_dpll" };
+
+PNAME(sw_aclk66_p) = { "dout_aclk66", "sclk_spll" };
+PNAME(aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66" };
+
+PNAME(sw_aclk200_fsys_p) = { "dout_aclk200_fsys", "sclk_spll"};
+PNAME(user_aclk200_fsys_p) = { "fin_pll", "mout_sw_aclk200_fsys" };
+
+PNAME(sw_aclk200_fsys2_p) = { "dout_aclk200_fsys2", "sclk_spll"};
+PNAME(user_aclk200_fsys2_p) = { "fin_pll", "mout_sw_aclk200_fsys2" };
+
+PNAME(sw_aclk200_p) = { "dout_aclk200", "sclk_spll"};
+PNAME(aclk200_disp1_p) = { "fin_pll", "mout_sw_aclk200" };
+
+PNAME(sw_aclk400_mscl_p) = { "dout_aclk400_mscl", "sclk_spll"};
+PNAME(user_aclk400_mscl_p) = { "fin_pll", "mout_sw_aclk400_mscl" };
+
+PNAME(sw_aclk333_p) = { "dout_aclk333", "sclk_spll"};
+PNAME(user_aclk333_p) = { "fin_pll", "mout_sw_aclk333" };
+
+PNAME(sw_aclk166_p) = { "dout_aclk166", "sclk_spll"};
+PNAME(user_aclk166_p) = { "fin_pll", "mout_sw_aclk166" };
+
+PNAME(sw_aclk266_p) = { "dout_aclk266", "sclk_spll"};
+PNAME(user_aclk266_p) = { "fin_pll", "mout_sw_aclk266" };
+
+PNAME(sw_aclk333_432_gscl_p) = { "dout_aclk333_432_gscl", "sclk_spll"};
+PNAME(user_aclk333_432_gscl_p) = { "fin_pll", "mout_sw_aclk333_432_gscl" };
+
+PNAME(sw_aclk300_gscl_p) = { "dout_aclk300_gscl", "sclk_spll"};
+PNAME(user_aclk300_gscl_p) = { "fin_pll", "mout_sw_aclk300_gscl" };
+
+PNAME(sw_aclk300_disp1_p) = { "dout_aclk300_disp1", "sclk_spll"};
+PNAME(user_aclk300_disp1_p) = { "fin_pll", "mout_sw_aclk300_disp1" };
+
+PNAME(sw_aclk300_jpeg_p) = { "dout_aclk300_jpeg", "sclk_spll"};
+PNAME(user_aclk300_jpeg_p) = { "fin_pll", "mout_sw_aclk300_jpeg" };
+
+PNAME(sw_aclk_g3d_p) = { "dout_aclk_g3d", "sclk_spll"};
+PNAME(user_aclk_g3d_p) = { "fin_pll", "mout_sw_aclk_g3d" };
+
+PNAME(sw_aclk266_g2d_p) = { "dout_aclk266_g2d", "sclk_spll"};
+PNAME(user_aclk266_g2d_p) = { "fin_pll", "mout_sw_aclk266_g2d" };
+
+PNAME(sw_aclk333_g2d_p) = { "dout_aclk333_g2d", "sclk_spll"};
+PNAME(user_aclk333_g2d_p) = { "fin_pll", "mout_sw_aclk333_g2d" };
+
+PNAME(audio0_p) = { "fin_pll", "cdclk0", "sclk_dpll", "sclk_mpll",
+ "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
+PNAME(audio1_p) = { "fin_pll", "cdclk1", "sclk_dpll", "sclk_mpll",
+ "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
+PNAME(audio2_p) = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll",
+ "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
+PNAME(spdif_p) = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2",
+ "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" };
+PNAME(hdmi_p) = { "sclk_hdmiphy", "dout_hdmi_pixel" };
+PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
+ "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
+
+/* fixed rate clocks generated outside the soc */
+struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
+ FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
+};
+
+/* fixed rate clocks generated inside the soc */
+struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = {
+ FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
+ FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
+ FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
+ FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
+ FRATE(none, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),
+};
+
+struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = {
+ FFACTOR(none, "sclk_hsic_12m", "fin_pll", 1, 2, 0),
+};
+
+struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
+ MUX(none, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2),
+ MUX(none, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2),
+ MUX(none, "mout_apll", apll_p, SRC_CPU, 0, 1),
+ MUX(none, "mout_cpu", cpu_p, SRC_CPU, 16, 1),
+ MUX(none, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
+ MUX(none, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1),
+
+ MUX(none, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
+
+ MUX_A(none, "mout_aclk400_mscl", group1_p,
+ SRC_TOP0, 4, 2, "aclk400_mscl"),
+ MUX(none, "mout_aclk200", group1_p, SRC_TOP0, 8, 2),
+ MUX(none, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2),
+ MUX(none, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2),
+
+ MUX(none, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2),
+ MUX(none, "mout_aclk66", group1_p, SRC_TOP1, 8, 2),
+ MUX(none, "mout_aclk266", group1_p, SRC_TOP1, 20, 2),
+ MUX(none, "mout_aclk166", group1_p, SRC_TOP1, 24, 2),
+ MUX(none, "mout_aclk333", group1_p, SRC_TOP1, 28, 2),
+
+ MUX(none, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2),
+ MUX(none, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2),
+ MUX(none, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1),
+ MUX(none, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2),
+ MUX(none, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2),
+ MUX(none, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2),
+
+ MUX(none, "mout_user_aclk400_mscl", user_aclk400_mscl_p,
+ SRC_TOP3, 4, 1),
+ MUX_A(none, "mout_aclk200_disp1", aclk200_disp1_p,
+ SRC_TOP3, 8, 1, "aclk200_disp1"),
+ MUX(none, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p,
+ SRC_TOP3, 12, 1),
+ MUX(none, "mout_user_aclk200_fsys", user_aclk200_fsys_p,
+ SRC_TOP3, 28, 1),
+
+ MUX(none, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p,
+ SRC_TOP4, 0, 1),
+ MUX(none, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1),
+ MUX(none, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1),
+ MUX(none, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1),
+ MUX(none, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1),
+
+ MUX(none, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1),
+ MUX(none, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1),
+ MUX(none, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1),
+ MUX_A(none, "mout_user_aclk_g3d", user_aclk_g3d_p,
+ SRC_TOP5, 16, 1, "aclkg3d"),
+ MUX(none, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p,
+ SRC_TOP5, 20, 1),
+ MUX(none, "mout_user_aclk300_disp1", user_aclk300_disp1_p,
+ SRC_TOP5, 24, 1),
+ MUX(none, "mout_user_aclk300_gscl", user_aclk300_gscl_p,
+ SRC_TOP5, 28, 1),
+
+ MUX(none, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1),
+ MUX(none, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1),
+ MUX(none, "sclk_spll", spll_p, SRC_TOP6, 8, 1),
+ MUX(none, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1),
+ MUX(none, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1),
+ MUX(none, "sclk_epll", epll_p, SRC_TOP6, 20, 1),
+ MUX(none, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1),
+ MUX(none, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1),
+
+ MUX(none, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1),
+ MUX(none, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1),
+ MUX(none, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p,
+ SRC_TOP10, 12, 1),
+ MUX(none, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1),
+
+ MUX(none, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p,
+ SRC_TOP11, 0, 1),
+ MUX(none, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1),
+ MUX(none, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1),
+ MUX(none, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1),
+ MUX(none, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1),
+
+ MUX(none, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1),
+ MUX(none, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1),
+ MUX(none, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1),
+ MUX(none, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1),
+ MUX(none, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p,
+ SRC_TOP12, 24, 1),
+ MUX(none, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
+
+ /* DISP1 Block */
+ MUX(none, "mout_fimd1", group3_p, SRC_DISP10, 4, 1),
+ MUX(none, "mout_mipi1", group2_p, SRC_DISP10, 16, 3),
+ MUX(none, "mout_dp1", group2_p, SRC_DISP10, 20, 3),
+ MUX(none, "mout_pixel", group2_p, SRC_DISP10, 24, 3),
+ MUX(none, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
+
+ /* MAU Block */
+ MUX(none, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3),
+
+ /* FSYS Block */
+ MUX(none, "mout_usbd301", group2_p, SRC_FSYS, 4, 3),
+ MUX(none, "mout_mmc0", group2_p, SRC_FSYS, 8, 3),
+ MUX(none, "mout_mmc1", group2_p, SRC_FSYS, 12, 3),
+ MUX(none, "mout_mmc2", group2_p, SRC_FSYS, 16, 3),
+ MUX(none, "mout_usbd300", group2_p, SRC_FSYS, 20, 3),
+ MUX(none, "mout_unipro", group2_p, SRC_FSYS, 24, 3),
+
+ /* PERIC Block */
+ MUX(none, "mout_uart0", group2_p, SRC_PERIC0, 4, 3),
+ MUX(none, "mout_uart1", group2_p, SRC_PERIC0, 8, 3),
+ MUX(none, "mout_uart2", group2_p, SRC_PERIC0, 12, 3),
+ MUX(none, "mout_uart3", group2_p, SRC_PERIC0, 16, 3),
+ MUX(none, "mout_pwm", group2_p, SRC_PERIC0, 24, 3),
+ MUX(none, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3),
+ MUX(none, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3),
+ MUX(none, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3),
+ MUX(none, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3),
+ MUX(none, "mout_spi0", group2_p, SRC_PERIC1, 20, 3),
+ MUX(none, "mout_spi1", group2_p, SRC_PERIC1, 24, 3),
+ MUX(none, "mout_spi2", group2_p, SRC_PERIC1, 28, 3),
+};
+
+struct samsung_div_clock exynos5420_div_clks[] __initdata = {
+ DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
+ DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
+ DIV(none, "armclk2", "div_arm", DIV_CPU0, 28, 3),
+ DIV(none, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3),
+ DIV(none, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
+
+ DIV(none, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
+ DIV(none, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
+ DIV(none, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
+ DIV(none, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
+ DIV(none, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
+
+ DIV(none, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
+ DIV_TOP1, 0, 3),
+ DIV(none, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
+ DIV(none, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
+ DIV(none, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
+ DIV(none, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
+
+ DIV(none, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3),
+ DIV(none, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
+ DIV(none, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
+ DIV(none, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
+ DIV_A(none, "dout_aclk300_disp1", "mout_aclk300_disp1",
+ DIV_TOP2, 24, 3, "aclk300_disp1"),
+ DIV(none, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
+
+ /* DISP1 Block */
+ DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
+ DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
+ DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
+ DIV(none, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
+
+ /* Audio Block */
+ DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
+ DIV(none, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
+
+ /* USB3.0 */
+ DIV(none, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
+ DIV(none, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
+ DIV(none, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
+ DIV(none, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
+
+ /* MMC */
+ DIV(none, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
+ DIV(none, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
+ DIV(none, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
+
+ DIV(none, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
+
+ /* UART and PWM */
+ DIV(none, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
+ DIV(none, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
+ DIV(none, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
+ DIV(none, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
+ DIV(none, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
+
+ /* SPI */
+ DIV(none, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
+ DIV(none, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
+ DIV(none, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
+
+ /* PCM */
+ DIV(none, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
+ DIV(none, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
+
+ /* Audio - I2S */
+ DIV(none, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
+ DIV(none, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
+ DIV(none, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
+ DIV(none, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
+ DIV(none, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
+
+ /* SPI Pre-Ratio */
+ DIV(none, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8),
+ DIV(none, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8),
+ DIV(none, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8),
+};
+
+struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
+ /* TODO: Re-verify the CG bits for all the gate clocks */
+ GATE_A(mct, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, "mct"),
+
+ GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
+ GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
+ GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
+
+ GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
+ GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
+ GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
+ GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
+ GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
+ GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "pclk66_gpio", "mout_sw_aclk66",
+ GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "aclk66_psgen", "mout_aclk66_psgen",
+ GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "aclk66_peric", "mout_aclk66_peric",
+ GATE_BUS_TOP, 11, 0, 0),
+ GATE(0, "aclk166", "mout_user_aclk166",
+ GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "aclk333", "mout_aclk333",
+ GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
+
+ /* sclk */
+ GATE(sclk_uart0, "sclk_uart0", "dout_uart0",
+ GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_uart1, "sclk_uart1", "dout_uart1",
+ GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_uart2, "sclk_uart2", "dout_uart2",
+ GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_uart3, "sclk_uart3", "dout_uart3",
+ GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_spi0, "sclk_spi0", "dout_pre_spi0",
+ GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_spi1, "sclk_spi1", "dout_pre_spi1",
+ GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_spi2, "sclk_spi2", "dout_pre_spi2",
+ GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_spdif, "sclk_spdif", "mout_spdif",
+ GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_pwm, "sclk_pwm", "dout_pwm",
+ GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_pcm1, "sclk_pcm1", "dout_pcm1",
+ GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_pcm2, "sclk_pcm2", "dout_pcm2",
+ GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_i2s1, "sclk_i2s1", "dout_i2s1",
+ GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_i2s2, "sclk_i2s2", "dout_i2s2",
+ GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
+
+ GATE(sclk_mmc0, "sclk_mmc0", "dout_mmc0",
+ GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_mmc1, "sclk_mmc1", "dout_mmc1",
+ GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_mmc2, "sclk_mmc2", "dout_mmc2",
+ GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_usbphy301, "sclk_usbphy301", "dout_usbphy301",
+ GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_usbphy300, "sclk_usbphy300", "dout_usbphy300",
+ GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_usbd300, "sclk_usbd300", "dout_usbd300",
+ GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_usbd301, "sclk_usbd301", "dout_usbd301",
+ GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
+
+ GATE(sclk_usbd301, "sclk_unipro", "dout_unipro",
+ SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
+
+ GATE(sclk_gscl_wa, "sclk_gscl_wa", "aclK333_432_gscl",
+ GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_gscl_wb, "sclk_gscl_wb", "aclk333_432_gscl",
+ GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0),
+
+ /* Display */
+ GATE(sclk_fimd1, "sclk_fimd1", "dout_fimd1",
+ GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_mipi1, "sclk_mipi1", "dout_mipi1",
+ GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
+ GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel",
+ GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_dp1, "sclk_dp1", "dout_dp1",
+ GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
+
+ /* Maudio Block */
+ GATE(sclk_maudio0, "sclk_maudio0", "dout_maudio0",
+ GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_maupcm0, "sclk_maupcm0", "dout_maupcm0",
+ GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
+ /* FSYS */
+ GATE(tsi, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
+ GATE(pdma0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
+ GATE(pdma1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
+ GATE(ufs, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
+ GATE(rtic, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
+ GATE(mmc0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
+ GATE(mmc1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
+ GATE(mmc2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
+ GATE(sromc, "sromc", "aclk200_fsys2",
+ GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0),
+ GATE(usbh20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0),
+ GATE(usbd300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0),
+ GATE(usbd301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0),
+
+ /* UART */
+ GATE(uart0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
+ GATE(uart1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
+ GATE_A(uart2, "uart2", "aclk66_peric",
+ GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"),
+ GATE(uart3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
+ /* I2C */
+ GATE(i2c0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
+ GATE(i2c1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
+ GATE(i2c2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
+ GATE(i2c3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
+ GATE(i2c4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0),
+ GATE(i2c5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0),
+ GATE(i2c6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0),
+ GATE(i2c7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0),
+ GATE(i2c_hdmi, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0, 0),
+ GATE(tsadc, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
+ /* SPI */
+ GATE(spi0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
+ GATE(spi1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
+ GATE(spi2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
+ GATE(keyif, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
+ /* I2S */
+ GATE(i2s1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
+ GATE(i2s2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
+ /* PCM */
+ GATE(pcm1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
+ GATE(pcm2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
+ /* PWM */
+ GATE(pwm, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
+ /* SPDIF */
+ GATE(spdif, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
+
+ GATE(i2c8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0),
+ GATE(i2c9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0),
+ GATE(i2c10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0),
+
+ GATE(chipid, "chipid", "aclk66_psgen",
+ GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0),
+ GATE(sysreg, "sysreg", "aclk66_psgen",
+ GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0),
+ GATE(tzpc0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0),
+ GATE(tzpc1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0),
+ GATE(tzpc2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0),
+ GATE(tzpc3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0),
+ GATE(tzpc4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0),
+ GATE(tzpc5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0),
+ GATE(tzpc6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0),
+ GATE(tzpc7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0),
+ GATE(tzpc8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0),
+ GATE(tzpc9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0),
+
+ GATE(hdmi_cec, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0, 0),
+ GATE(seckey, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
+ GATE(wdt, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0),
+ GATE(rtc, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0),
+ GATE(tmu, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0),
+ GATE(tmu_gpu, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0),
+
+ GATE(gscl0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
+ GATE(gscl1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
+ GATE(clk_3aa, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0),
+
+ GATE(smmu_3aa, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0, 0),
+ GATE(smmu_fimcl0, "smmu_fimcl0", "aclk333_432_gscl",
+ GATE_IP_GSCL1, 3, 0, 0),
+ GATE(smmu_fimcl1, "smmu_fimcl1", "aclk333_432_gscl",
+ GATE_IP_GSCL1, 4, 0, 0),
+ GATE(smmu_gscl0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0, 0),
+ GATE(smmu_gscl1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0, 0),
+ GATE(gscl_wa, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0),
+ GATE(gscl_wb, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0),
+ GATE(smmu_fimcl3, "smmu_fimcl3,", "aclk333_432_gscl",
+ GATE_IP_GSCL1, 16, 0, 0),
+ GATE(fimc_lite3, "fimc_lite3", "aclk333_432_gscl",
+ GATE_IP_GSCL1, 17, 0, 0),
+
+ GATE(fimd1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
+ GATE(dsim1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
+ GATE(dp1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
+ GATE(mixer, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
+ GATE(hdmi, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
+ GATE(smmu_fimd1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0, 0),
+
+ GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
+ GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
+ GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
+
+ GATE(g3d, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
+
+ GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
+ GATE(jpeg, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
+ GATE(jpeg2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
+ GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
+ GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
+ GATE(smmu_jpeg, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
+ GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
+
+ GATE(mscl0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
+ GATE(mscl1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
+ GATE(mscl2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
+ GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0),
+ GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0),
+ GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0),
+};
+
+static __initdata struct of_device_id ext_clk_match[] = {
+ { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
+ { },
+};
+
+/* register exynos5420 clocks */
+void __init exynos5420_clk_init(struct device_node *np)
+{
+ void __iomem *reg_base;
+ struct clk *apll, *bpll, *cpll, *dpll, *epll, *ipll, *kpll, *mpll;
+ struct clk *rpll, *spll, *vpll;
+
+ if (np) {
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+ } else {
+ panic("%s: unable to determine soc\n", __func__);
+ }
+
+ samsung_clk_init(np, reg_base, nr_clks,
+ exynos5420_clk_regs, ARRAY_SIZE(exynos5420_clk_regs),
+ NULL, 0);
+ samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks,
+ ARRAY_SIZE(exynos5420_fixed_rate_ext_clks),
+ ext_clk_match);
+
+ apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
+ reg_base + 0x100);
+ bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
+ reg_base + 0x20110);
+ cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
+ reg_base + 0x10120);
+ dpll = samsung_clk_register_pll35xx("fout_dpll", "fin_pll",
+ reg_base + 0x10128);
+ epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
+ reg_base + 0x10130);
+ ipll = samsung_clk_register_pll35xx("fout_ipll", "fin_pll",
+ reg_base + 0x10150);
+ kpll = samsung_clk_register_pll35xx("fout_kpll", "fin_pll",
+ reg_base + 0x28100);
+ mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
+ reg_base + 0x10180);
+ rpll = samsung_clk_register_pll36xx("fout_rpll", "fin_pll",
+ reg_base + 0x10140);
+ spll = samsung_clk_register_pll35xx("fout_spll", "fin_pll",
+ reg_base + 0x10160);
+ vpll = samsung_clk_register_pll35xx("fout_vpll", "fin_pll",
+ reg_base + 0x10170);
+
+ samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks,
+ ARRAY_SIZE(exynos5420_fixed_rate_clks));
+ samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks,
+ ARRAY_SIZE(exynos5420_fixed_factor_clks));
+ samsung_clk_register_mux(exynos5420_mux_clks,
+ ARRAY_SIZE(exynos5420_mux_clks));
+ samsung_clk_register_div(exynos5420_div_clks,
+ ARRAY_SIZE(exynos5420_div_clks));
+ samsung_clk_register_gate(exynos5420_gate_clks,
+ ARRAY_SIZE(exynos5420_gate_clks));
+}
+CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init);
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 662fcc065821f3100e55e014b2ce1801966e87e8..a70480409ea526a9233e9af6025c50ade2497167 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -400,18 +400,6 @@ static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
return IRQ_HANDLED;
}
-static struct irqaction mct_tick0_event_irq = {
- .name = "mct_tick0_irq",
- .flags = IRQF_TIMER | IRQF_NOBALANCING,
- .handler = exynos4_mct_tick_isr,
-};
-
-static struct irqaction mct_tick1_event_irq = {
- .name = "mct_tick1_irq",
- .flags = IRQF_TIMER | IRQF_NOBALANCING,
- .handler = exynos4_mct_tick_isr,
-};
-
static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
{
struct mct_clock_event_device *mevt;
@@ -435,16 +423,15 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
if (mct_int_type == MCT_INT_SPI) {
- if (cpu == 0) {
- mct_tick0_event_irq.dev_id = mevt;
- evt->irq = mct_irqs[MCT_L0_IRQ];
- setup_irq(evt->irq, &mct_tick0_event_irq);
- } else {
- mct_tick1_event_irq.dev_id = mevt;
- evt->irq = mct_irqs[MCT_L1_IRQ];
- setup_irq(evt->irq, &mct_tick1_event_irq);
- irq_set_affinity(evt->irq, cpumask_of(1));
+ evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
+ if (request_irq(evt->irq, exynos4_mct_tick_isr,
+ IRQF_TIMER | IRQF_NOBALANCING,
+ evt->name, mevt)) {
+ pr_err("exynos-mct: cannot register IRQ %d\n",
+ evt->irq);
+ return -EIO;
}
+ irq_set_affinity(evt->irq, cpumask_of(cpu));
} else {
enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
}
@@ -454,13 +441,9 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
static void exynos4_local_timer_stop(struct clock_event_device *evt)
{
- unsigned int cpu = smp_processor_id();
evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
if (mct_int_type == MCT_INT_SPI)
- if (cpu == 0)
- remove_irq(evt->irq, &mct_tick0_event_irq);
- else
- remove_irq(evt->irq, &mct_tick1_event_irq);
+ free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
else
disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
}
diff --git a/drivers/iommu/msm_iommu_dev.c b/drivers/iommu/msm_iommu_dev.c
index 8e8fb079852d22ca124a5c0ff7bbce9d3f5ec365..9144a6beed922a70c995c09099f822f02baddca2 100644
--- a/drivers/iommu/msm_iommu_dev.c
+++ b/drivers/iommu/msm_iommu_dev.c
@@ -29,7 +29,6 @@
#include <mach/iommu_hw-8xxx.h>
#include <mach/iommu.h>
-#include <mach/clk.h>
struct iommu_ctx_iter_data {
/* input */
@@ -160,7 +159,7 @@ static int msm_iommu_probe(struct platform_device *pdev)
goto fail;
}
- ret = clk_enable(iommu_pclk);
+ ret = clk_prepare_enable(iommu_pclk);
if (ret)
goto fail_enable;
@@ -168,9 +167,9 @@ static int msm_iommu_probe(struct platform_device *pdev)
if (!IS_ERR(iommu_clk)) {
if (clk_get_rate(iommu_clk) == 0)
- clk_set_min_rate(iommu_clk, 1);
+ clk_set_rate(iommu_clk, 1);
- ret = clk_enable(iommu_clk);
+ ret = clk_prepare_enable(iommu_clk);
if (ret) {
clk_put(iommu_clk);
goto fail_pclk;
@@ -261,7 +260,7 @@ static int msm_iommu_probe(struct platform_device *pdev)
clk_put(iommu_clk);
}
fail_pclk:
- clk_disable(iommu_pclk);
+ clk_disable_unprepare(iommu_pclk);
fail_enable:
clk_put(iommu_pclk);
fail:
@@ -275,8 +274,11 @@ static int msm_iommu_remove(struct platform_device *pdev)
drv = platform_get_drvdata(pdev);
if (drv) {
- if (drv->clk)
+ if (drv->clk) {
+ clk_unprepare(drv->clk);
clk_put(drv->clk);
+ }
+ clk_unprepare(drv->pclk);
clk_put(drv->pclk);
memset(drv, 0, sizeof(*drv));
kfree(drv);
@@ -314,14 +316,14 @@ static int msm_iommu_ctx_probe(struct platform_device *pdev)
INIT_LIST_HEAD(&ctx_drvdata->attached_elm);
platform_set_drvdata(pdev, ctx_drvdata);
- ret = clk_enable(drvdata->pclk);
+ ret = clk_prepare_enable(drvdata->pclk);
if (ret)
goto fail;
if (drvdata->clk) {
- ret = clk_enable(drvdata->clk);
+ ret = clk_prepare_enable(drvdata->clk);
if (ret) {
- clk_disable(drvdata->pclk);
+ clk_disable_unprepare(drvdata->pclk);
goto fail;
}
}
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index 0ee4a57fe6b28d03e7cdb6e87cbac897f429d0a5..b900de4e7e942c38c6bd5c78c521325619b83aca 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -1268,10 +1268,18 @@ msmsdcc_probe(struct platform_device *pdev)
goto clk_put;
}
+ ret = clk_prepare(host->pclk);
+ if (ret)
+ goto clk_put;
+
+ ret = clk_prepare(host->clk);
+ if (ret)
+ goto clk_unprepare_p;
+
/* Enable clocks */
ret = msmsdcc_enable_clocks(host);
if (ret)
- goto clk_put;
+ goto clk_unprepare;
host->pclk_rate = clk_get_rate(host->pclk);
host->clk_rate = clk_get_rate(host->clk);
@@ -1386,6 +1394,10 @@ msmsdcc_probe(struct platform_device *pdev)
free_irq(host->stat_irq, host);
clk_disable:
msmsdcc_disable_clocks(host, 0);
+ clk_unprepare:
+ clk_unprepare(host->clk);
+ clk_unprepare_p:
+ clk_unprepare(host->pclk);
clk_put:
clk_put(host->clk);
pclk_put:
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 2d76f66a2e0b90c3a3ac1cfe9036a42840c15a43..5f58cf0e96e2e1e55660677193bd0b142eecf771 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -941,3 +941,121 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
.label = "exynos5250-gpio-ctrl3",
},
};
+
+/* pin banks of exynos5420 pin-controller 0 */
+static struct samsung_pin_bank exynos5420_pin_banks0[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
+};
+
+/* pin banks of exynos5420 pin-controller 1 */
+static struct samsung_pin_bank exynos5420_pin_banks1[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
+ EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
+ EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
+ EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
+ EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
+ EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
+ EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
+ EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
+ EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
+ EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
+ EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
+};
+
+/* pin banks of exynos5420 pin-controller 2 */
+static struct samsung_pin_bank exynos5420_pin_banks2[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
+ EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
+ EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
+ EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
+};
+
+/* pin banks of exynos5420 pin-controller 3 */
+static struct samsung_pin_bank exynos5420_pin_banks3[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
+ EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
+ EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
+ EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
+ EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
+};
+
+/* pin banks of exynos5420 pin-controller 4 */
+static struct samsung_pin_bank exynos5420_pin_banks4[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
+ * four gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 data */
+ .pin_banks = exynos5420_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
+ .geint_con = EXYNOS_GPIO_ECON_OFFSET,
+ .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
+ .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
+ .weint_con = EXYNOS_WKUP_ECON_OFFSET,
+ .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
+ .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
+ .svc = EXYNOS_SVC_OFFSET,
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .label = "exynos5420-gpio-ctrl0",
+ }, {
+ /* pin-controller instance 1 data */
+ .pin_banks = exynos5420_pin_banks1,
+ .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
+ .geint_con = EXYNOS_GPIO_ECON_OFFSET,
+ .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
+ .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
+ .svc = EXYNOS_SVC_OFFSET,
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .label = "exynos5420-gpio-ctrl1",
+ }, {
+ /* pin-controller instance 2 data */
+ .pin_banks = exynos5420_pin_banks2,
+ .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
+ .geint_con = EXYNOS_GPIO_ECON_OFFSET,
+ .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
+ .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
+ .svc = EXYNOS_SVC_OFFSET,
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .label = "exynos5420-gpio-ctrl2",
+ }, {
+ /* pin-controller instance 3 data */
+ .pin_banks = exynos5420_pin_banks3,
+ .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
+ .geint_con = EXYNOS_GPIO_ECON_OFFSET,
+ .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
+ .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
+ .svc = EXYNOS_SVC_OFFSET,
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .label = "exynos5420-gpio-ctrl3",
+ }, {
+ /* pin-controller instance 4 data */
+ .pin_banks = exynos5420_pin_banks4,
+ .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
+ .geint_con = EXYNOS_GPIO_ECON_OFFSET,
+ .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
+ .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
+ .svc = EXYNOS_SVC_OFFSET,
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .label = "exynos5420-gpio-ctrl4",
+ },
+};
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index e67ff1b8042ce99fd27b26a8ef6fb2c1d8603902..0a6c720b6655ba1860d282a453073ac89da9881e 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -1113,6 +1113,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
.data = (void *)exynos4x12_pin_ctrl },
{ .compatible = "samsung,exynos5250-pinctrl",
.data = (void *)exynos5250_pin_ctrl },
+ { .compatible = "samsung,exynos5420-pinctrl",
+ .data = (void *)exynos5420_pin_ctrl },
#endif
#ifdef CONFIG_PINCTRL_S3C64XX
{ .compatible = "samsung,s3c64xx-pinctrl",
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index 79fcc2076c00d4919df10def1474a5f1cda10bf3..11bb75ba81a949e9bf33caa04e97847c494e905f 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -254,6 +254,7 @@ struct samsung_pmx_func {
extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
+extern struct samsung_pin_ctrl exynos5420_pin_ctrl[];
extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[];
extern struct samsung_pin_ctrl s3c2412_pin_ctrl[];
extern struct samsung_pin_ctrl s3c2416_pin_ctrl[];
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index b11e99797fd8016815feb7d9999b0f35df62eb3b..2c6cfb3cf0327789929aa6ce3f38040a03e99327 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -408,9 +408,9 @@ static void msm_init_clock(struct uart_port *port)
{
struct msm_port *msm_port = UART_TO_MSM(port);
- clk_enable(msm_port->clk);
+ clk_prepare_enable(msm_port->clk);
if (!IS_ERR(msm_port->pclk))
- clk_enable(msm_port->pclk);
+ clk_prepare_enable(msm_port->pclk);
msm_serial_set_mnd_regs(port);
}
@@ -486,7 +486,7 @@ static void msm_shutdown(struct uart_port *port)
msm_port->imr = 0;
msm_write(port, 0, UART_IMR); /* disable interrupts */
- clk_disable(msm_port->clk);
+ clk_disable_unprepare(msm_port->clk);
free_irq(port->irq, port);
}
@@ -688,14 +688,14 @@ static void msm_power(struct uart_port *port, unsigned int state,
switch (state) {
case 0:
- clk_enable(msm_port->clk);
+ clk_prepare_enable(msm_port->clk);
if (!IS_ERR(msm_port->pclk))
- clk_enable(msm_port->pclk);
+ clk_prepare_enable(msm_port->pclk);
break;
case 3:
- clk_disable(msm_port->clk);
+ clk_disable_unprepare(msm_port->clk);
if (!IS_ERR(msm_port->pclk))
- clk_disable(msm_port->pclk);
+ clk_disable_unprepare(msm_port->pclk);
break;
default:
printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state);
@@ -884,19 +884,22 @@ static int __init msm_serial_probe(struct platform_device *pdev)
msm_port->is_uartdm = 0;
if (msm_port->is_uartdm) {
- msm_port->clk = clk_get(&pdev->dev, "gsbi_uart_clk");
- msm_port->pclk = clk_get(&pdev->dev, "gsbi_pclk");
+ msm_port->clk = devm_clk_get(&pdev->dev, "gsbi_uart_clk");
+ msm_port->pclk = devm_clk_get(&pdev->dev, "gsbi_pclk");
} else {
- msm_port->clk = clk_get(&pdev->dev, "uart_clk");
+ msm_port->clk = devm_clk_get(&pdev->dev, "uart_clk");
msm_port->pclk = ERR_PTR(-ENOENT);
}
- if (unlikely(IS_ERR(msm_port->clk) || (IS_ERR(msm_port->pclk) &&
- msm_port->is_uartdm)))
- return PTR_ERR(msm_port->clk);
+ if (IS_ERR(msm_port->clk))
+ return PTR_ERR(msm_port->clk);
+
+ if (msm_port->is_uartdm) {
+ if (IS_ERR(msm_port->pclk))
+ return PTR_ERR(msm_port->pclk);
- if (msm_port->is_uartdm)
clk_set_rate(msm_port->clk, 1843200);
+ }
port->uartclk = clk_get_rate(msm_port->clk);
printk(KERN_INFO "uartclk = %d\n", port->uartclk);
@@ -919,9 +922,9 @@ static int __init msm_serial_probe(struct platform_device *pdev)
static int msm_serial_remove(struct platform_device *pdev)
{
- struct msm_port *msm_port = platform_get_drvdata(pdev);
+ struct uart_port *port = platform_get_drvdata(pdev);
- clk_put(msm_port->clk);
+ uart_remove_one_port(&msm_uart_driver, port);
return 0;
}
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 81ebc86a9e23480fe2498093e96a44429f1d880a..376079b9bd75f77bac213cfcb8e419740bc12a4d 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1713,9 +1713,7 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
#endif
-#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \
- defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) || \
- defined(CONFIG_SOC_EXYNOS5440)
+#if defined(CONFIG_ARCH_EXYNOS)
static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
.info = &(struct s3c24xx_uart_info) {
.name = "Samsung Exynos4 UART",
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 15641861994920b4c68c184ce57844e93b11bb8e..7477e0ea5cdb886607e023ae06ce8cc92bb2edde 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -146,6 +146,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCRFDR] = sci_reg_invalid,
[SCSPTR] = sci_reg_invalid,
[SCLSR] = sci_reg_invalid,
+ [HSSRR] = sci_reg_invalid,
},
/*
@@ -165,6 +166,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCRFDR] = sci_reg_invalid,
[SCSPTR] = sci_reg_invalid,
[SCLSR] = sci_reg_invalid,
+ [HSSRR] = sci_reg_invalid,
},
/*
@@ -183,6 +185,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCRFDR] = sci_reg_invalid,
[SCSPTR] = sci_reg_invalid,
[SCLSR] = sci_reg_invalid,
+ [HSSRR] = sci_reg_invalid,
},
/*
@@ -201,6 +204,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCRFDR] = { 0x3c, 16 },
[SCSPTR] = sci_reg_invalid,
[SCLSR] = sci_reg_invalid,
+ [HSSRR] = sci_reg_invalid,
},
/*
@@ -220,6 +224,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCRFDR] = sci_reg_invalid,
[SCSPTR] = { 0x20, 16 },
[SCLSR] = { 0x24, 16 },
+ [HSSRR] = sci_reg_invalid,
},
/*
@@ -238,6 +243,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCRFDR] = sci_reg_invalid,
[SCSPTR] = sci_reg_invalid,
[SCLSR] = sci_reg_invalid,
+ [HSSRR] = sci_reg_invalid,
},
/*
@@ -256,6 +262,26 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCRFDR] = sci_reg_invalid,
[SCSPTR] = { 0x20, 16 },
[SCLSR] = { 0x24, 16 },
+ [HSSRR] = sci_reg_invalid,
+ },
+
+ /*
+ * Common HSCIF definitions.
+ */
+ [SCIx_HSCIF_REGTYPE] = {
+ [SCSMR] = { 0x00, 16 },
+ [SCBRR] = { 0x04, 8 },
+ [SCSCR] = { 0x08, 16 },
+ [SCxTDR] = { 0x0c, 8 },
+ [SCxSR] = { 0x10, 16 },
+ [SCxRDR] = { 0x14, 8 },
+ [SCFCR] = { 0x18, 16 },
+ [SCFDR] = { 0x1c, 16 },
+ [SCTFDR] = sci_reg_invalid,
+ [SCRFDR] = sci_reg_invalid,
+ [SCSPTR] = { 0x20, 16 },
+ [SCLSR] = { 0x24, 16 },
+ [HSSRR] = { 0x40, 16 },
},
/*
@@ -275,6 +301,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCRFDR] = sci_reg_invalid,
[SCSPTR] = sci_reg_invalid,
[SCLSR] = { 0x24, 16 },
+ [HSSRR] = sci_reg_invalid,
},
/*
@@ -294,6 +321,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCRFDR] = { 0x20, 16 },
[SCSPTR] = { 0x24, 16 },
[SCLSR] = { 0x28, 16 },
+ [HSSRR] = sci_reg_invalid,
},
/*
@@ -313,6 +341,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
[SCRFDR] = sci_reg_invalid,
[SCSPTR] = sci_reg_invalid,
[SCLSR] = sci_reg_invalid,
+ [HSSRR] = sci_reg_invalid,
},
};
@@ -374,6 +403,9 @@ static int sci_probe_regmap(struct plat_sci_port *cfg)
*/
cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
break;
+ case PORT_HSCIF:
+ cfg->regtype = SCIx_HSCIF_REGTYPE;
+ break;
default:
printk(KERN_ERR "Can't probe register map for given port\n");
return -EINVAL;
@@ -1798,6 +1830,42 @@ static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
return ((freq + 16 * bps) / (32 * bps) - 1);
}
+/* calculate sample rate, BRR, and clock select for HSCIF */
+static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
+ int *brr, unsigned int *srr,
+ unsigned int *cks)
+{
+ int sr, c, br, err;
+ int min_err = 1000; /* 100% */
+
+ /* Find the combination of sample rate and clock select with the
+ smallest deviation from the desired baud rate. */
+ for (sr = 8; sr <= 32; sr++) {
+ for (c = 0; c <= 3; c++) {
+ /* integerized formulas from HSCIF documentation */
+ br = freq / (sr * (1 << (2 * c + 1)) * bps) - 1;
+ if (br < 0 || br > 255)
+ continue;
+ err = freq / ((br + 1) * bps * sr *
+ (1 << (2 * c + 1)) / 1000) - 1000;
+ if (min_err > err) {
+ min_err = err;
+ *brr = br;
+ *srr = sr - 1;
+ *cks = c;
+ }
+ }
+ }
+
+ if (min_err == 1000) {
+ WARN_ON(1);
+ /* use defaults */
+ *brr = 255;
+ *srr = 15;
+ *cks = 0;
+ }
+}
+
static void sci_reset(struct uart_port *port)
{
struct plat_sci_reg *reg;
@@ -1819,8 +1887,9 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
{
struct sci_port *s = to_sci_port(port);
struct plat_sci_reg *reg;
- unsigned int baud, smr_val, max_baud, cks;
+ unsigned int baud, smr_val, max_baud, cks = 0;
int t = -1;
+ unsigned int srr = 15;
/*
* earlyprintk comes here early on with port->uartclk set to zero.
@@ -1833,8 +1902,17 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
max_baud = port->uartclk ? port->uartclk / 16 : 115200;
baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
- if (likely(baud && port->uartclk))
- t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
+ if (likely(baud && port->uartclk)) {
+ if (s->cfg->scbrr_algo_id == SCBRR_ALGO_6) {
+ sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
+ &cks);
+ } else {
+ t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud,
+ port->uartclk);
+ for (cks = 0; t >= 256 && cks <= 3; cks++)
+ t >>= 2;
+ }
+ }
sci_port_enable(s);
@@ -1853,15 +1931,15 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
uart_update_timeout(port, termios->c_cflag, baud);
- for (cks = 0; t >= 256 && cks <= 3; cks++)
- t >>= 2;
-
dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
__func__, smr_val, cks, t, s->cfg->scscr);
if (t >= 0) {
serial_port_out(port, SCSMR, (smr_val & ~3) | cks);
serial_port_out(port, SCBRR, t);
+ reg = sci_getreg(port, HSSRR);
+ if (reg->size)
+ serial_port_out(port, HSSRR, srr | HSCIF_SRE);
udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
} else
serial_port_out(port, SCSMR, smr_val);
@@ -1947,6 +2025,8 @@ static const char *sci_type(struct uart_port *port)
return "scifa";
case PORT_SCIFB:
return "scifb";
+ case PORT_HSCIF:
+ return "hscif";
}
return NULL;
@@ -1960,7 +2040,10 @@ static inline unsigned long sci_port_size(struct uart_port *port)
* from platform resource data at such a time that ports begin to
* behave more erratically.
*/
- return 64;
+ if (port->type == PORT_HSCIF)
+ return 96;
+ else
+ return 64;
}
static int sci_remap_port(struct uart_port *port)
@@ -2085,6 +2168,9 @@ static int sci_init_single(struct platform_device *dev,
case PORT_SCIFB:
port->fifosize = 256;
break;
+ case PORT_HSCIF:
+ port->fifosize = 128;
+ break;
case PORT_SCIFA:
port->fifosize = 64;
break;
@@ -2325,7 +2411,7 @@ static inline int sci_probe_earlyprintk(struct platform_device *pdev)
#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
static char banner[] __initdata =
- KERN_INFO "SuperH SCI(F) driver initialized\n";
+ KERN_INFO "SuperH (H)SCI(F) driver initialized\n";
static struct uart_driver sci_uart_driver = {
.owner = THIS_MODULE,
@@ -2484,4 +2570,4 @@ module_exit(sci_exit);
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:sh-sci");
MODULE_AUTHOR("Paul Mundt");
-MODULE_DESCRIPTION("SuperH SCI(F) serial driver");
+MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index 749fbf41fb6f5d8b192d0705f9306860c120d804..d08f33435e96e67f9b61389e176f624d64a2f95d 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -514,13 +514,13 @@ static int msm_otg_suspend(struct msm_otg *motg)
motg->pdata->otg_control == OTG_PMIC_CONTROL)
writel(readl(USB_PHY_CTRL) | PHY_RETEN, USB_PHY_CTRL);
- clk_disable(motg->pclk);
- clk_disable(motg->clk);
+ clk_disable_unprepare(motg->pclk);
+ clk_disable_unprepare(motg->clk);
if (motg->core_clk)
- clk_disable(motg->core_clk);
+ clk_disable_unprepare(motg->core_clk);
if (!IS_ERR(motg->pclk_src))
- clk_disable(motg->pclk_src);
+ clk_disable_unprepare(motg->pclk_src);
if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
motg->pdata->otg_control == OTG_PMIC_CONTROL) {
@@ -552,12 +552,12 @@ static int msm_otg_resume(struct msm_otg *motg)
return 0;
if (!IS_ERR(motg->pclk_src))
- clk_enable(motg->pclk_src);
+ clk_prepare_enable(motg->pclk_src);
- clk_enable(motg->pclk);
- clk_enable(motg->clk);
+ clk_prepare_enable(motg->pclk);
+ clk_prepare_enable(motg->clk);
if (motg->core_clk)
- clk_enable(motg->core_clk);
+ clk_prepare_enable(motg->core_clk);
if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
motg->pdata->otg_control == OTG_PMIC_CONTROL) {
@@ -1468,7 +1468,7 @@ static int __init msm_otg_probe(struct platform_device *pdev)
if (IS_ERR(motg->pclk_src))
goto put_clk;
clk_set_rate(motg->pclk_src, INT_MAX);
- clk_enable(motg->pclk_src);
+ clk_prepare_enable(motg->pclk_src);
} else
motg->pclk_src = ERR_PTR(-ENOENT);
@@ -1511,8 +1511,8 @@ static int __init msm_otg_probe(struct platform_device *pdev)
goto free_regs;
}
- clk_enable(motg->clk);
- clk_enable(motg->pclk);
+ clk_prepare_enable(motg->clk);
+ clk_prepare_enable(motg->pclk);
ret = msm_hsusb_init_vddcx(motg, 1);
if (ret) {
@@ -1532,7 +1532,7 @@ static int __init msm_otg_probe(struct platform_device *pdev)
}
if (motg->core_clk)
- clk_enable(motg->core_clk);
+ clk_prepare_enable(motg->core_clk);
writel(0, USB_USBINTR);
writel(0, USB_OTGSC);
@@ -1579,8 +1579,8 @@ static int __init msm_otg_probe(struct platform_device *pdev)
free_irq:
free_irq(motg->irq, motg);
disable_clks:
- clk_disable(motg->pclk);
- clk_disable(motg->clk);
+ clk_disable_unprepare(motg->pclk);
+ clk_disable_unprepare(motg->clk);
ldo_exit:
msm_hsusb_ldo_init(motg, 0);
vddcx_exit:
@@ -1593,7 +1593,7 @@ static int __init msm_otg_probe(struct platform_device *pdev)
clk_put(motg->pclk);
put_pclk_src:
if (!IS_ERR(motg->pclk_src)) {
- clk_disable(motg->pclk_src);
+ clk_disable_unprepare(motg->pclk_src);
clk_put(motg->pclk_src);
}
put_clk:
@@ -1643,12 +1643,12 @@ static int msm_otg_remove(struct platform_device *pdev)
if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
dev_err(phy->dev, "Unable to suspend PHY\n");
- clk_disable(motg->pclk);
- clk_disable(motg->clk);
+ clk_disable_unprepare(motg->pclk);
+ clk_disable_unprepare(motg->clk);
if (motg->core_clk)
- clk_disable(motg->core_clk);
+ clk_disable_unprepare(motg->core_clk);
if (!IS_ERR(motg->pclk_src)) {
- clk_disable(motg->pclk_src);
+ clk_disable_unprepare(motg->pclk_src);
clk_put(motg->pclk_src);
}
msm_hsusb_ldo_init(motg, 0);
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index eb763adf98158d113655233b21e7f9fe1ebd2cce..d34049712a4d7cee24958816840ca1c843e0541f 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -5,7 +5,7 @@
#include <linux/sh_dma.h>
/*
- * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
+ * Generic header for SuperH (H)SCI(F) (used by sh/sh64/h8300 and related parts)
*/
#define SCIx_NOT_SUPPORTED (-1)
@@ -16,6 +16,7 @@ enum {
SCBRR_ALGO_3, /* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */
SCBRR_ALGO_4, /* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */
SCBRR_ALGO_5, /* (((clk * 1000 / 32) / bps) - 1) */
+ SCBRR_ALGO_6, /* HSCIF variable sample rate algorithm */
};
#define SCSCR_TIE (1 << 7)
@@ -37,7 +38,7 @@ enum {
#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
-/* SCxSR SCIF */
+/* SCxSR SCIF, HSCIF */
#define SCIF_ER 0x0080
#define SCIF_TEND 0x0040
#define SCIF_TDFE 0x0020
@@ -55,6 +56,9 @@ enum {
#define SCSPTR_SPB2IO (1 << 1)
#define SCSPTR_SPB2DT (1 << 0)
+/* HSSRR HSCIF */
+#define HSCIF_SRE 0x8000
+
/* Offsets into the sci_port->irqs array */
enum {
SCIx_ERI_IRQ,
@@ -90,6 +94,7 @@ enum {
SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
SCIx_SH4_SCIF_FIFODATA_REGTYPE,
SCIx_SH7705_SCIF_REGTYPE,
+ SCIx_HSCIF_REGTYPE,
SCIx_NR_REGTYPES,
};
@@ -115,6 +120,7 @@ enum {
SCSMR, SCBRR, SCSCR, SCxSR,
SCFCR, SCFDR, SCxTDR, SCxRDR,
SCLSR, SCTFDR, SCRFDR, SCSPTR,
+ HSSRR,
SCIx_NR_REGS,
};
@@ -137,7 +143,7 @@ struct plat_sci_port {
unsigned long mapbase; /* resource base */
unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
unsigned int gpios[SCIx_NR_FNS]; /* SCK, RXD, TXD, CTS, RTS */
- unsigned int type; /* SCI / SCIF / IRDA */
+ unsigned int type; /* SCI / SCIF / IRDA / HSCIF */
upf_t flags; /* UPF_* flags */
unsigned long capabilities; /* Port features/capabilities */
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index c8eaeb5465ef76e4ec8992f45e6523a72ebc258c..9119cc0977bf42a36f2ae8aa51123c99b0b5f9d7 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -229,4 +229,7 @@
/* Freescale lpuart */
#define PORT_LPUART 103
+/* SH-SCI */
+#define PORT_HSCIF 104
+
#endif /* _UAPILINUX_SERIAL_CORE_H */