Commit 43fa561f authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amdgpu: remove duplicate cg/pg wrapper functions 



Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Acked-by: default avatarChristian <König&lt;christian.koenig@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 10b3f45c

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+2 −2
Original line number Diff line number Diff line
@@ -222,10 +222,10 @@ enum amdgpu_kiq_irq { 
	AMDGPU_CP_KIQ_IRQ_LAST

};



int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,

int amdgpu_device_ip_set_clockgating_state(void *dev,

					   enum amd_ip_block_type block_type,

					   enum amd_clockgating_state state);

int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,

int amdgpu_device_ip_set_powergating_state(void *dev,

					   enum amd_ip_block_type block_type,

					   enum amd_powergating_state state);

void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

+0 −44
Original line number Diff line number Diff line
@@ -108,48 +108,6 @@ static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device, 
	WARN(1, "Invalid indirect register space");

}



static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,

				  enum amd_ip_block_type block_type,

				  enum amd_clockgating_state state)

{

	CGS_FUNC_ADEV;

	int i, r = -1;



	for (i = 0; i < adev->num_ip_blocks; i++) {

		if (!adev->ip_blocks[i].status.valid)

			continue;



		if (adev->ip_blocks[i].version->type == block_type) {

			r = adev->ip_blocks[i].version->funcs->set_clockgating_state(

								(void *)adev,

									state);

			break;

		}

	}

	return r;

}



static int amdgpu_cgs_set_powergating_state(struct cgs_device *cgs_device,

				  enum amd_ip_block_type block_type,

				  enum amd_powergating_state state)

{

	CGS_FUNC_ADEV;

	int i, r = -1;



	for (i = 0; i < adev->num_ip_blocks; i++) {

		if (!adev->ip_blocks[i].status.valid)

			continue;



		if (adev->ip_blocks[i].version->type == block_type) {

			r = adev->ip_blocks[i].version->funcs->set_powergating_state(

								(void *)adev,

									state);

			break;

		}

	}

	return r;

}



static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)

{

	CGS_FUNC_ADEV;
@@ -490,8 +448,6 @@ static const struct cgs_ops amdgpu_cgs_ops = { 
	.read_ind_register = amdgpu_cgs_read_ind_register,

	.write_ind_register = amdgpu_cgs_write_ind_register,

	.get_firmware_info = amdgpu_cgs_get_firmware_info,

	.set_powergating_state = amdgpu_cgs_set_powergating_state,

	.set_clockgating_state = amdgpu_cgs_set_clockgating_state,

};



struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+4 −2
Original line number Diff line number Diff line
@@ -1039,10 +1039,11 @@ static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { 
 * the hardware IP specified.

 * Returns the error code from the last instance.

 */

int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,

int amdgpu_device_ip_set_clockgating_state(void *dev,

					   enum amd_ip_block_type block_type,

					   enum amd_clockgating_state state)

{

	struct amdgpu_device *adev = dev;

	int i, r = 0;



	for (i = 0; i < adev->num_ip_blocks; i++) {
@@ -1072,10 +1073,11 @@ int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev, 
 * the hardware IP specified.

 * Returns the error code from the last instance.

 */

int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,

int amdgpu_device_ip_set_powergating_state(void *dev,

					   enum amd_ip_block_type block_type,

					   enum amd_powergating_state state)

{

	struct amdgpu_device *adev = dev;

	int i, r = 0;



	for (i = 0; i < adev->num_ip_blocks; i++) {

drivers/gpu/drm/amd/include/cgs_common.h

+0 −31
Original line number Diff line number Diff line
@@ -42,20 +42,6 @@ enum cgs_ind_reg { 
	CGS_IND_REG__AUDIO_ENDPT

};



/**

 * enum cgs_engine - Engines that can be statically power-gated

 */

enum cgs_engine {

	CGS_ENGINE__UVD,

	CGS_ENGINE__VCE,

	CGS_ENGINE__VP8,

	CGS_ENGINE__ACP_DMA,

	CGS_ENGINE__ACP_DSP0,

	CGS_ENGINE__ACP_DSP1,

	CGS_ENGINE__ISP,

	/* ... */

};



/*

 * enum cgs_ucode_id - Firmware types for different IPs

 */
@@ -152,15 +138,6 @@ typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device, 
				     enum cgs_ucode_id type,

				     struct cgs_firmware_info *info);





typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device,

				  enum amd_ip_block_type block_type,

				  enum amd_powergating_state state);



typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device,

				  enum amd_ip_block_type block_type,

				  enum amd_clockgating_state state);



struct cgs_ops {

	/* MMIO access */

	cgs_read_register_t read_register;
@@ -169,9 +146,6 @@ struct cgs_ops { 
	cgs_write_ind_register_t write_ind_register;

	/* Firmware Info */

	cgs_get_firmware_info get_firmware_info;

	/* cg pg interface*/

	cgs_set_powergating_state set_powergating_state;

	cgs_set_clockgating_state set_clockgating_state;

};



struct cgs_os_ops; /* To be define in OS-specific CGS header */
@@ -200,10 +174,5 @@ struct cgs_device 


#define cgs_get_firmware_info(dev, type, info)	\

	CGS_CALL(get_firmware_info, dev, type, info)

#define cgs_set_powergating_state(dev, block_type, state)	\

	CGS_CALL(set_powergating_state, dev, block_type, state)

#define cgs_set_clockgating_state(dev, block_type, state)	\

	CGS_CALL(set_clockgating_state, dev, block_type, state)





#endif /* _CGS_COMMON_H */

drivers/gpu/drm/amd/powerplay/amd_powerplay.c

+4 −4
Original line number Diff line number Diff line
@@ -288,10 +288,10 @@ static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr, 
		if (*level & profile_mode_mask) {

			hwmgr->saved_dpm_level = hwmgr->dpm_level;

			hwmgr->en_umd_pstate = true;

			cgs_set_clockgating_state(hwmgr->device,

			amdgpu_device_ip_set_clockgating_state(hwmgr->adev,

						AMD_IP_BLOCK_TYPE_GFX,

						AMD_CG_STATE_UNGATE);

			cgs_set_powergating_state(hwmgr->device,

			amdgpu_device_ip_set_powergating_state(hwmgr->adev,

					AMD_IP_BLOCK_TYPE_GFX,

					AMD_PG_STATE_UNGATE);

		}
@@ -301,10 +301,10 @@ static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr, 
			if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)

				*level = hwmgr->saved_dpm_level;

			hwmgr->en_umd_pstate = false;

			cgs_set_clockgating_state(hwmgr->device,

			amdgpu_device_ip_set_clockgating_state(hwmgr->adev,

					AMD_IP_BLOCK_TYPE_GFX,

					AMD_CG_STATE_GATE);

			cgs_set_powergating_state(hwmgr->device,

			amdgpu_device_ip_set_powergating_state(hwmgr->adev,

					AMD_IP_BLOCK_TYPE_GFX,

					AMD_PG_STATE_GATE);

		}