Loading arch/arm/mm/proc-v7.S +4 −5 Original line number Diff line number Diff line Loading @@ -409,14 +409,13 @@ __v7_setup: bl v7_flush_dcache_louis ldmia r12, {r0-r5, r7, r9, r11, lr} mrc p15, 0, r0, c0, c0, 0 @ read main ID register and r10, r0, #0xff000000 @ ARM? and r10, r9, #0xff000000 @ ARM? teq r10, #0x41000000 bne __errata_finish and r3, r0, #0x00f00000 @ variant and r6, r0, #0x0000000f @ revision and r3, r9, #0x00f00000 @ variant and r6, r9, #0x0000000f @ revision orr r6, r6, r3, lsr #20-4 @ combine variant and revision ubfx r0, r0, #4, #12 @ primary part number ubfx r0, r9, #4, #12 @ primary part number /* Cortex-A8 Errata */ ldr r10, =0x00000c08 @ Cortex-A8 primary part number Loading Loading
arch/arm/mm/proc-v7.S +4 −5 Original line number Diff line number Diff line Loading @@ -409,14 +409,13 @@ __v7_setup: bl v7_flush_dcache_louis ldmia r12, {r0-r5, r7, r9, r11, lr} mrc p15, 0, r0, c0, c0, 0 @ read main ID register and r10, r0, #0xff000000 @ ARM? and r10, r9, #0xff000000 @ ARM? teq r10, #0x41000000 bne __errata_finish and r3, r0, #0x00f00000 @ variant and r6, r0, #0x0000000f @ revision and r3, r9, #0x00f00000 @ variant and r6, r9, #0x0000000f @ revision orr r6, r6, r3, lsr #20-4 @ combine variant and revision ubfx r0, r0, #4, #12 @ primary part number ubfx r0, r9, #4, #12 @ primary part number /* Cortex-A8 Errata */ ldr r10, =0x00000c08 @ Cortex-A8 primary part number Loading