Commit 44bf8704 authored by Kalyan Thota's avatar Kalyan Thota Committed by Rob Clark
Browse files

drm/msm/disp/dpu1: set default group ID for CTL. 



New required programming in CTL for SC7280. Group ID informs
HW of which VM owns that CTL. Force this group ID to
default/disabled until virtualization support is enabled in SW.

Changes in v1:
 - Fix documentation and add descritpion for the change (Stephen)

Signed-off-by: default avatarKalyan Thota <quic_kalyant@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1635510619-6715-1-git-send-email-quic_kalyant@quicinc.com


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 92cb1bed

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -45,7 +45,7 @@ 
	(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))

	(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))





#define CTL_SC7280_MASK \

#define CTL_SC7280_MASK \

	(BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE))

	(BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG))





#define MERGE_3D_SM8150_MASK (0)

#define MERGE_3D_SM8150_MASK (0)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

+4 −1
Original line number Original line Diff line number Diff line
@@ -179,13 +179,16 @@ enum { 




/**

/**

 * CTL sub-blocks

 * CTL sub-blocks

 * @DPU_CTL_SPLIT_DISPLAY       CTL supports video mode split display

 * @DPU_CTL_SPLIT_DISPLAY:	CTL supports video mode split display

 * @DPU_CTL_FETCH_ACTIVE:	Active CTL for fetch HW (SSPPs)

 * @DPU_CTL_VM_CFG:		CTL config to support multiple VMs

 * @DPU_CTL_MAX

 * @DPU_CTL_MAX

 */

 */

enum {

enum {

	DPU_CTL_SPLIT_DISPLAY = 0x1,

	DPU_CTL_SPLIT_DISPLAY = 0x1,

	DPU_CTL_ACTIVE_CFG,

	DPU_CTL_ACTIVE_CFG,

	DPU_CTL_FETCH_ACTIVE,

	DPU_CTL_FETCH_ACTIVE,

	DPU_CTL_VM_CFG,

	DPU_CTL_MAX

	DPU_CTL_MAX

};

};

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

+8 −0
Original line number Original line Diff line number Diff line
@@ -36,6 +36,7 @@ 
#define  MERGE_3D_IDX   23

#define  MERGE_3D_IDX   23

#define  INTF_IDX       31

#define  INTF_IDX       31

#define CTL_INVALID_BIT                 0xffff

#define CTL_INVALID_BIT                 0xffff

#define CTL_DEFAULT_GROUP_ID		0xf





static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19,

static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19,

	CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0,

	CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0,
@@ -498,6 +499,13 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, 
	u32 intf_active = 0;

	u32 intf_active = 0;

	u32 mode_sel = 0;

	u32 mode_sel = 0;





	/* CTL_TOP[31:28] carries group_id to collate CTL paths

	 * per VM. Explicitly disable it until VM support is

	 * added in SW. Power on reset value is not disable.

	 */

	if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))

		mode_sel = CTL_DEFAULT_GROUP_ID  << 28;



	if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)

	if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)

		mode_sel |= BIT(17);

		mode_sel |= BIT(17);