Commit 44c4abe0 authored by John Garry's avatar John Garry Committed by Martin K. Petersen
Browse files

scsi: hisi_sas: fix HBA SAS addr endianness for v1 hw 



The endianness for the SAS address in the TX_ID_DWORD registers is set
incorrectly.  We see errors like this in the boot log for v2 hw (which
would have the same issue as v1 hw):

[    7.583284] sas: target proto 0x0 at 50000d1108e7923f:0x1f not handled

This is due to the host SAS addr not matching the PHY SAS addr in the
expander host-attached phy discovery responses.

To fix, we byte swap the SAS addr from BE to LE (which is the endianness
of the SAS controller).

Signed-off-by: default avatarJohn Garry <john.garry@huawei.com>
Signed-off-by: default avatarXiang Chen <chenxiang66@hisilicon.com>
Reviewed-by: default avatarHannes Reinecke <hare@suse.com>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent d82debec

drivers/scsi/hisi_sas/hisi_sas_v1_hw.c

+4 −4
Original line number Diff line number Diff line
@@ -490,13 +490,13 @@ static void config_id_frame_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 
	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,

			__swab32(identify_buffer[0]));

	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,

			identify_buffer[2]);

			__swab32(identify_buffer[1]));

	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,

			identify_buffer[1]);

			__swab32(identify_buffer[2]));

	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,

			identify_buffer[4]);

			__swab32(identify_buffer[3]));

	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,

			identify_buffer[3]);

			__swab32(identify_buffer[4]));

	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,

			__swab32(identify_buffer[5]));

}