Loading drivers/video/omap2/dss/dsi.c +10 −5 Original line number Original line Diff line number Diff line Loading @@ -3813,18 +3813,22 @@ static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev) static void dsi_config_vp_sync_events(struct platform_device *dsidev) static void dsi_config_vp_sync_events(struct platform_device *dsidev) { { struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); bool vsync_end = dsi->vm_timings.vp_vsync_end; bool sync_end; bool hsync_end = dsi->vm_timings.vp_hsync_end; u32 r; u32 r; if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE) sync_end = true; else sync_end = false; r = dsi_read_reg(dsidev, DSI_CTRL); r = dsi_read_reg(dsidev, DSI_CTRL); r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ r = FLD_MOD(r, vsync_end, 16, 16); /* VP_VSYNC_END */ r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */ r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ r = FLD_MOD(r, hsync_end, 18, 18); /* VP_HSYNC_END */ r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */ dsi_write_reg(dsidev, DSI_CTRL, r); dsi_write_reg(dsidev, DSI_CTRL, r); } } Loading Loading @@ -4171,11 +4175,12 @@ static void dsi_proto_timings(struct platform_device *dsidev) int vfp = dsi->vm_timings.vfp; int vfp = dsi->vm_timings.vfp; int vbp = dsi->vm_timings.vbp; int vbp = dsi->vm_timings.vbp; int window_sync = dsi->vm_timings.window_sync; int window_sync = dsi->vm_timings.window_sync; bool hsync_end = dsi->vm_timings.vp_hsync_end; bool hsync_end; struct omap_video_timings *timings = &dsi->timings; struct omap_video_timings *timings = &dsi->timings; int bpp = dsi_get_pixel_size(dsi->pix_fmt); int bpp = dsi_get_pixel_size(dsi->pix_fmt); int tl, t_he, width_bytes; int tl, t_he, width_bytes; hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE; t_he = hsync_end ? t_he = hsync_end ? ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; Loading include/video/omapdss.h +10 −3 Original line number Original line Diff line number Diff line Loading @@ -257,6 +257,15 @@ void rfbi_bus_unlock(void); /* DSI */ /* DSI */ enum omap_dss_dsi_trans_mode { /* Sync Pulses: both sync start and end packets sent */ OMAP_DSS_DSI_PULSE_MODE, /* Sync Events: only sync start packets sent */ OMAP_DSS_DSI_EVENT_MODE, /* Burst: only sync start packets sent, pixels are time compressed */ OMAP_DSS_DSI_BURST_MODE, }; struct omap_dss_dsi_videomode_timings { struct omap_dss_dsi_videomode_timings { /* DSI video mode blanking data */ /* DSI video mode blanking data */ /* Unit: byte clock cycles */ /* Unit: byte clock cycles */ Loading @@ -274,9 +283,7 @@ struct omap_dss_dsi_videomode_timings { int hbp_blanking_mode; int hbp_blanking_mode; int hfp_blanking_mode; int hfp_blanking_mode; /* Video port sync events */ enum omap_dss_dsi_trans_mode trans_mode; bool vp_vsync_end; bool vp_hsync_end; bool ddr_clk_always_on; bool ddr_clk_always_on; int window_sync; int window_sync; Loading Loading
drivers/video/omap2/dss/dsi.c +10 −5 Original line number Original line Diff line number Diff line Loading @@ -3813,18 +3813,22 @@ static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev) static void dsi_config_vp_sync_events(struct platform_device *dsidev) static void dsi_config_vp_sync_events(struct platform_device *dsidev) { { struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); bool vsync_end = dsi->vm_timings.vp_vsync_end; bool sync_end; bool hsync_end = dsi->vm_timings.vp_hsync_end; u32 r; u32 r; if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE) sync_end = true; else sync_end = false; r = dsi_read_reg(dsidev, DSI_CTRL); r = dsi_read_reg(dsidev, DSI_CTRL); r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ r = FLD_MOD(r, vsync_end, 16, 16); /* VP_VSYNC_END */ r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */ r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ r = FLD_MOD(r, hsync_end, 18, 18); /* VP_HSYNC_END */ r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */ dsi_write_reg(dsidev, DSI_CTRL, r); dsi_write_reg(dsidev, DSI_CTRL, r); } } Loading Loading @@ -4171,11 +4175,12 @@ static void dsi_proto_timings(struct platform_device *dsidev) int vfp = dsi->vm_timings.vfp; int vfp = dsi->vm_timings.vfp; int vbp = dsi->vm_timings.vbp; int vbp = dsi->vm_timings.vbp; int window_sync = dsi->vm_timings.window_sync; int window_sync = dsi->vm_timings.window_sync; bool hsync_end = dsi->vm_timings.vp_hsync_end; bool hsync_end; struct omap_video_timings *timings = &dsi->timings; struct omap_video_timings *timings = &dsi->timings; int bpp = dsi_get_pixel_size(dsi->pix_fmt); int bpp = dsi_get_pixel_size(dsi->pix_fmt); int tl, t_he, width_bytes; int tl, t_he, width_bytes; hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE; t_he = hsync_end ? t_he = hsync_end ? ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; Loading
include/video/omapdss.h +10 −3 Original line number Original line Diff line number Diff line Loading @@ -257,6 +257,15 @@ void rfbi_bus_unlock(void); /* DSI */ /* DSI */ enum omap_dss_dsi_trans_mode { /* Sync Pulses: both sync start and end packets sent */ OMAP_DSS_DSI_PULSE_MODE, /* Sync Events: only sync start packets sent */ OMAP_DSS_DSI_EVENT_MODE, /* Burst: only sync start packets sent, pixels are time compressed */ OMAP_DSS_DSI_BURST_MODE, }; struct omap_dss_dsi_videomode_timings { struct omap_dss_dsi_videomode_timings { /* DSI video mode blanking data */ /* DSI video mode blanking data */ /* Unit: byte clock cycles */ /* Unit: byte clock cycles */ Loading @@ -274,9 +283,7 @@ struct omap_dss_dsi_videomode_timings { int hbp_blanking_mode; int hbp_blanking_mode; int hfp_blanking_mode; int hfp_blanking_mode; /* Video port sync events */ enum omap_dss_dsi_trans_mode trans_mode; bool vp_vsync_end; bool vp_hsync_end; bool ddr_clk_always_on; bool ddr_clk_always_on; int window_sync; int window_sync; Loading