Commit 47c02af7 authored by Lewis Huang's avatar Lewis Huang Committed by Alex Deucher
Browse files

drm/amd/display: skip program clock when allow seamless boot 



[Why]
Driver program dpp clock calculate by pipe split config but hw config is single pipe.

[How]
Skip programming clock when allow seamless boot.
After porgramming pipe config, seamless boot flag will be clear.

Signed-off-by: default avatarLewis Huang <Lewis.Huang@amd.com>
Reviewed-by: default avatarEric Yang <eric.yang2@amd.com>
Acked-by: default avatarWayne Lin <waynelin@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d5433a9f

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+13 −2
Original line number Diff line number Diff line
@@ -1206,13 +1206,24 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason) 
{

	const struct dc *dc = link->dc;

	bool ret;

	bool can_apply_seamless_boot = false;

	int i;



	for (i = 0; i < dc->current_state->stream_count; i++) {

		if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {

			can_apply_seamless_boot = true;

			break;

		}

	}



	/* get out of low power state */

	if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)

		clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);



	ret = dc_link_detect_helper(link, reason);



	/* Go back to power optimized state */

	if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)

		clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);



	return ret;