Commit 490ddccb authored May 18, 2023 by Saaem Rizvi Committed by Alex Deucher Jun 09, 2023

drm/amd/display: Wrong index type for pipe iterator



[Why and How]
Type mismatch in index and pipe count might cause an infinite loop. code
Change should resolve this issue.

Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Saaem Rizvi <syedsaaem.rizvi@amd.com>
Reviewed-by: Josip Pavic <Josip.Pavic@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 0baae624

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -392,7 +392,7 @@ void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)

	void dcn314_resync_fifo_dccg_dio(struct dce_hwseq hws, struct dc dc, struct dc_state *context)		void dcn314_resync_fifo_dccg_dio(struct dce_hwseq hws, struct dc dc, struct dc_state *context)
	{		{
	uint8_t i;		unsigned int i;
	struct pipe_ctx *pipe = NULL;		struct pipe_ctx *pipe = NULL;
	bool otg_disabled[MAX_PIPES] = {false};		bool otg_disabled[MAX_PIPES] = {false};

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -1201,7 +1201,7 @@ void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)

	void dcn32_resync_fifo_dccg_dio(struct dce_hwseq hws, struct dc dc, struct dc_state *context)		void dcn32_resync_fifo_dccg_dio(struct dce_hwseq hws, struct dc dc, struct dc_state *context)
	{		{
	uint8_t i;		unsigned int i;
	struct pipe_ctx *pipe = NULL;		struct pipe_ctx *pipe = NULL;
	bool otg_disabled[MAX_PIPES] = {false};		bool otg_disabled[MAX_PIPES] = {false};