Commit 4b91ac9e authored by Iswara Nagulendran's avatar Iswara Nagulendran Committed by Alex Deucher
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drm/amd/display: Fix primary EDP link detection 



[HOW&WHY]
EDP link detection must
be updated to support a primary EDP with a
link index of greater than 0.

* SWDEV-342936 - dc: DSC bringup for SAG 1.5

[WHY]
SmartAccess Graphics 1.5 (a.k.a SmartMux 1.5)
requires seamless switching between GPUs
with DSC enabled.

[HOW]
Moved DSC programming to
apply_single_control_ctx_to_hw before the stream
enablement logic to ensure the CRC checker provides valid
values for non-black frames
allowing the system to come out of forced PSR on
d2i.

Added additional logic to both generate a black
frame through setVisibility calls and keep track
of the CRCs values for this black frame when
coming out of forced PSR.

Updating logic for DalRegKey_DisableDSC to disable
DSC on EDP and all ports for systems.

[CLEANED]
dc: Moved DSC programming to before stream enablement

[HOW&WHY]
Moved DSC programming to
apply_single_control_ctx_to_hw before the stream
enablement logic.

Co-authored-by: default avatarsregolui <sregolui@amd.com>
Reviewed-by: default avatarJayendran Ramani <Jayendran.Ramani@amd.com>
Reviewed-by: default avatarHarry Vanzylldejong <Harry.Vanzylldejong@amd.com>
Acked-by: default avatarBrian Chang <Brian.Chang@amd.com>
Signed-off-by: default avatarsregolui <sregolui@amd.com>
Signed-off-by: default avatarIswara Nagulendran <Iswara.Nagulendran@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b1bdb5eb

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+0 −12
Original line number Diff line number Diff line
@@ -4303,18 +4303,6 @@ void core_link_enable_stream( 
		if (pipe_ctx->stream->dpms_off)

			return;



		/* Have to setup DSC before DIG FE and BE are connected (which happens before the

		 * link training). This is to make sure the bandwidth sent to DIG BE won't be

		 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag

		 * will be automatically set at a later time when the video is enabled

		 * (DP_VID_STREAM_EN = 1).

		 */

		if (pipe_ctx->stream->timing.flags.DSC) {

			if (dc_is_dp_signal(pipe_ctx->stream->signal) ||

					dc_is_virtual_signal(pipe_ctx->stream->signal))

				dp_set_dsc_enable(pipe_ctx, true);

		}



		status = enable_link(state, pipe_ctx);



		if (status != DC_OK) {

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+13 −0
Original line number Diff line number Diff line
@@ -1577,6 +1577,19 @@ static enum dc_status apply_single_controller_ctx_to_hw( 
	if (dc_is_dp_signal(pipe_ctx->stream->signal))

		dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);



	/* Have to setup DSC before DIG FE and BE are connected (which happens before the

	 * link training). This is to make sure the bandwidth sent to DIG BE won't be

	 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag

	 * will be automatically set at a later time when the video is enabled

	 * (DP_VID_STREAM_EN = 1).

	 */

	if (pipe_ctx->stream->timing.flags.DSC) {

		if (dc_is_dp_signal(pipe_ctx->stream->signal) ||

			dc_is_virtual_signal(pipe_ctx->stream->signal))

			dp_set_dsc_enable(pipe_ctx, true);



	}



	if (!stream->dpms_off) {

		if (dc->hwss.update_phy_state)

			dc->hwss.update_phy_state(context, pipe_ctx, TX_ON_SYMCLK_ON);