Commit 4d319ed6 authored by Boyuan Zhang's avatar Boyuan Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: rename macro for VCN2.0 2.5 and 3.0 



Rename SOC15_DPG_MODE_OFFSET_2_0, RREG32_SOC15_DPG_MODE_2_0 and
WREG32_SOC15_DPG_MODE_2_0 for VCN2.0, VCN2.5 and VCN3.0.
These three macros are used VCN2.0, VCN2.5 and VCN3.0, therefore rename
it to be a general name.

Signed-off-by: default avatarBoyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: default avatarJames Zhu <james.zhu@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 914b5f53

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+3 −3
Original line number Diff line number Diff line
@@ -88,7 +88,7 @@ 
			(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); 		\

	} while (0)



#define SOC15_DPG_MODE_OFFSET_2_0(ip, inst_idx, reg) 						\

#define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) 						\

	({											\

		uint32_t internal_reg_offset, addr;						\

		bool video_range, video1_range, aon_range, aon1_range;				\
@@ -121,7 +121,7 @@ 
		internal_reg_offset >>= 2;							\

	})



#define RREG32_SOC15_DPG_MODE_2_0(inst_idx, offset, mask_en) 					\

#define RREG32_SOC15_DPG_MODE(inst_idx, offset, mask_en) 					\

	({											\

		WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, 					\

			(0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT |				\
@@ -130,7 +130,7 @@ 
		RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA);				\

	})



#define WREG32_SOC15_DPG_MODE_2_0(inst_idx, offset, value, mask_en, indirect)			\

#define WREG32_SOC15_DPG_MODE(inst_idx, offset, value, mask_en, indirect)			\

	do {											\

		if (!indirect) {								\

			WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA, value);			\

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

+43 −43
Original line number Diff line number Diff line
@@ -382,91 +382,91 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec 
	/* cache window 0: fw */

	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {

		if (!indirect) {

			WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

			WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

				UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),

				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);

			WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

			WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

				UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),

				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);

			WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

			WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

				UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);

		} else {

			WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

			WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

				UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);

			WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

			WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

				UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);

			WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

			WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

				UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);

		}

		offset = 0;

	} else {

		WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

			UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),

			lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);

		WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

			UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),

			upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);

		offset = size;

		WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

			UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),

			AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);

	}



	if (!indirect)

		WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

			UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);

	else

		WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

			UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);



	/* cache window 1: stack */

	if (!indirect) {

		WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

			UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),

			lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);

		WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

			UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),

			upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);

		WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

			UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);

	} else {

		WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

			UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);

		WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

			UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);

		WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

			UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);

	}

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);



	/* cache window 2: context */

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),

		lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),

		upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);



	/* non-cache window */

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),

		lower_32_bits(adev->vcn.inst->fw_shared_gpu_addr), 0, indirect);

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),

		upper_32_bits(adev->vcn.inst->fw_shared_gpu_addr), 0, indirect);

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0),

		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);



	/* VCN global tiling registers */

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);

}
@@ -615,19 +615,19 @@ static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 
		 UVD_CGC_CTRL__WCB_MODE_MASK |

		 UVD_CGC_CTRL__VCPU_MODE_MASK |

		 UVD_CGC_CTRL__SCPU_MODE_MASK);

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);



	/* turn off clock gating */

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);



	/* turn on SUVD clock gating */

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);



	/* turn on sw mode in UVD_SUVD_CGC_CTRL */

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);

}
@@ -810,11 +810,11 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect) 
	tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);

	tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;

	tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);



	/* disable master interupt */

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);



	/* setup mmUVD_LMI_CTRL */
@@ -826,28 +826,28 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect) 
		UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |

		(8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |

		0x00100000L);

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);



	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_MPC_CNTL),

		0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);



	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_MPC_SET_MUXA0),

		((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |

		 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |

		 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |

		 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);



	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_MPC_SET_MUXB0),

		((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |

		 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |

		 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |

		 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);



	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_MPC_SET_MUX),

		((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |

		 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
@@ -855,22 +855,22 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect) 


	vcn_v2_0_mc_resume_dpg_mode(adev, indirect);



	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);



	/* release VCPU reset to boot */

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);



	/* enable LMI MC and UMC channels */

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_LMI_CTRL2),

		0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect);



	/* enable master interrupt */

	WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_MASTINT_EN),

		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

+47 −47
Original line number Diff line number Diff line
@@ -443,7 +443,7 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev) 
	}

}



static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)

void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)

{

	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);

	uint32_t offset;
@@ -451,91 +451,91 @@ static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx 
	/* cache window 0: fw */

	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {

		if (!indirect) {

			WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

			WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

				VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),

				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);

			WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

			WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

				VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),

				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);

			WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

			WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

				VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);

		} else {

			WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

			WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

				VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);

			WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

			WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

				VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);

			WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

			WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

				VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);

		}

		offset = 0;

	} else {

		WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

			VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),

			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

		WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

			VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),

			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);

		offset = size;

		WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

			VCN, 0, mmUVD_VCPU_CACHE_OFFSET0),

			AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);

	}



	if (!indirect)

		WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

			VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);

	else

		WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

			VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);



	/* cache window 1: stack */

	if (!indirect) {

		WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

			VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),

			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

		WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

			VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),

			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

		WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

			VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);

	} else {

		WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

			VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);

		WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

			VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);

		WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

		WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

			VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);

	}

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);



	/* cache window 2: context */

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),

		lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),

		upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);



	/* non-cache window */

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),

		lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),

		upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0),

		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);



	/* VCN global tiling registers */

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);

}
@@ -657,7 +657,7 @@ static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev) 
	}

}



static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,

void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,

		uint8_t sram_sel, int inst_idx, uint8_t indirect)

{

	uint32_t reg_data = 0;
@@ -689,19 +689,19 @@ static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev, 
		 UVD_CGC_CTRL__WCB_MODE_MASK |

		 UVD_CGC_CTRL__VCPU_MODE_MASK |

		 UVD_CGC_CTRL__MMSCH_MODE_MASK);

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);



	/* turn off clock gating */

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);



	/* turn on SUVD clock gating */

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);



	/* turn on sw mode in UVD_SUVD_CGC_CTRL */

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);

}
@@ -792,11 +792,11 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo 
	tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);

	tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;

	tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);



	/* disable master interupt */

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect);



	/* setup mmUVD_LMI_CTRL */
@@ -808,28 +808,28 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo 
		UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |

		(8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |

		0x00100000L);

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);



	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_MPC_CNTL),

		0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);



	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_MPC_SET_MUXA0),

		((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |

		 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |

		 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |

		 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);



	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_MPC_SET_MUXB0),

		((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |

		 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |

		 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |

		 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);



	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_MPC_SET_MUX),

		((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |

		 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
@@ -837,26 +837,26 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo 


	vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);



	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);



	/* enable LMI MC and UMC channels */

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect);



	/* unblock VCPU register access */

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect);



	tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);

	tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);



	/* enable master interrupt */

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, 0, mmUVD_MASTINT_EN),

		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
@@ -1300,7 +1300,7 @@ static int vcn_v2_5_sriov_start(struct amdgpu_device *adev) 
	return vcn_v2_5_mmsch_start(adev, &adev->virt.mm_table);

}



static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)

int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)

{

	int ret_code = 0;

	uint32_t tmp;

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

+44 −44

File changed.

Preview size limit exceeded, changes collapsed.