Commit 4d6b228d authored by Luis R. Rodriguez's avatar Luis R. Rodriguez Committed by John W. Linville
Browse files

ath9k: use ath_hw for DPRINTF() and debug init/exit 



DPRINTF() is used in hw specific related code, as such
ensure we don't rely on the private driver core ath_softc
struct when calling it. Drivers can then implement their
own DPRINTF() as they see fit.

Signed-off-by: default avatarLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent d519e17e

drivers/net/wireless/ath/ath9k/ahb.c

+1 −1
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ static bool ath_ahb_eeprom_read(struct ath_hw *ah, u32 off, u16 *data) 


	pdata = (struct ath9k_platform_data *) pdev->dev.platform_data;

	if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {

		DPRINTF(ah->ah_sc, ATH_DBG_FATAL,

		DPRINTF(ah, ATH_DBG_FATAL,

			"%s: flash read failed, offset %08x is out of range\n",

				__func__, off);

		return false;

drivers/net/wireless/ath/ath9k/ani.c

+22 −22
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah, 
		}

	}



	DPRINTF(ah->ah_sc, ATH_DBG_ANI,

	DPRINTF(ah, ATH_DBG_ANI,

		"No more channel states left. Using channel 0\n");



	return 0;
@@ -47,7 +47,7 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah, 
		u32 level = param;



		if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {

			DPRINTF(ah->ah_sc, ATH_DBG_ANI,

			DPRINTF(ah, ATH_DBG_ANI,

				"level out of range (%u > %u)\n",

				level,

				(unsigned)ARRAY_SIZE(ah->totalSizeDesired));
@@ -152,7 +152,7 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah, 
		u32 level = param;



		if (level >= ARRAY_SIZE(firstep)) {

			DPRINTF(ah->ah_sc, ATH_DBG_ANI,

			DPRINTF(ah, ATH_DBG_ANI,

				"level out of range (%u > %u)\n",

				level,

				(unsigned) ARRAY_SIZE(firstep));
@@ -174,7 +174,7 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah, 
		u32 level = param;



		if (level >= ARRAY_SIZE(cycpwrThr1)) {

			DPRINTF(ah->ah_sc, ATH_DBG_ANI,

			DPRINTF(ah, ATH_DBG_ANI,

				"level out of range (%u > %u)\n",

				level,

				(unsigned)
@@ -194,23 +194,23 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah, 
	case ATH9K_ANI_PRESENT:

		break;

	default:

		DPRINTF(ah->ah_sc, ATH_DBG_ANI,

		DPRINTF(ah, ATH_DBG_ANI,

			"invalid cmd %u\n", cmd);

		return false;

	}



	DPRINTF(ah->ah_sc, ATH_DBG_ANI, "ANI parameters:\n");

	DPRINTF(ah->ah_sc, ATH_DBG_ANI,

	DPRINTF(ah, ATH_DBG_ANI, "ANI parameters:\n");

	DPRINTF(ah, ATH_DBG_ANI,

		"noiseImmunityLevel=%d, spurImmunityLevel=%d, "

		"ofdmWeakSigDetectOff=%d\n",

		aniState->noiseImmunityLevel, aniState->spurImmunityLevel,

		!aniState->ofdmWeakSigDetectOff);

	DPRINTF(ah->ah_sc, ATH_DBG_ANI,

	DPRINTF(ah, ATH_DBG_ANI,

		"cckWeakSigThreshold=%d, "

		"firstepLevel=%d, listenTime=%d\n",

		aniState->cckWeakSigThreshold, aniState->firstepLevel,

		aniState->listenTime);

	DPRINTF(ah->ah_sc, ATH_DBG_ANI,

	DPRINTF(ah, ATH_DBG_ANI,

		"cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",

		aniState->cycleCount, aniState->ofdmPhyErrCount,

		aniState->cckPhyErrCount);
@@ -240,7 +240,7 @@ static void ath9k_ani_restart(struct ath_hw *ah) 


	if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {

		aniState->ofdmPhyErrBase = 0;

		DPRINTF(ah->ah_sc, ATH_DBG_ANI,

		DPRINTF(ah, ATH_DBG_ANI,

			"OFDM Trigger is too high for hw counters\n");

	} else {

		aniState->ofdmPhyErrBase =
@@ -248,13 +248,13 @@ static void ath9k_ani_restart(struct ath_hw *ah) 
	}

	if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {

		aniState->cckPhyErrBase = 0;

		DPRINTF(ah->ah_sc, ATH_DBG_ANI,

		DPRINTF(ah, ATH_DBG_ANI,

			"CCK Trigger is too high for hw counters\n");

	} else {

		aniState->cckPhyErrBase =

			AR_PHY_COUNTMAX - aniState->cckTrigHigh;

	}

	DPRINTF(ah->ah_sc, ATH_DBG_ANI,

	DPRINTF(ah, ATH_DBG_ANI,

		"Writing ofdmbase=%u   cckbase=%u\n",

		aniState->ofdmPhyErrBase,

		aniState->cckPhyErrBase);
@@ -475,7 +475,7 @@ void ath9k_ani_reset(struct ath_hw *ah) 


	if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION

	    && ah->opmode != NL80211_IFTYPE_ADHOC) {

		DPRINTF(ah->ah_sc, ATH_DBG_ANI,

		DPRINTF(ah, ATH_DBG_ANI,

			"Reset ANI state opmode %u\n", ah->opmode);

		ah->stats.ast_ani_reset++;
@@ -569,7 +569,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, 
	if (phyCnt1 < aniState->ofdmPhyErrBase ||

	    phyCnt2 < aniState->cckPhyErrBase) {

		if (phyCnt1 < aniState->ofdmPhyErrBase) {

			DPRINTF(ah->ah_sc, ATH_DBG_ANI,

			DPRINTF(ah, ATH_DBG_ANI,

				"phyCnt1 0x%x, resetting "

				"counter value to 0x%x\n",

				phyCnt1, aniState->ofdmPhyErrBase);
@@ -579,7 +579,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, 
				  AR_PHY_ERR_OFDM_TIMING);

		}

		if (phyCnt2 < aniState->cckPhyErrBase) {

			DPRINTF(ah->ah_sc, ATH_DBG_ANI,

			DPRINTF(ah, ATH_DBG_ANI,

				"phyCnt2 0x%x, resetting "

				"counter value to 0x%x\n",

				phyCnt2, aniState->cckPhyErrBase);
@@ -624,7 +624,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, 


void ath9k_enable_mib_counters(struct ath_hw *ah)

{

	DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n");

	DPRINTF(ah, ATH_DBG_ANI, "Enable MIB counters\n");



	ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
@@ -640,7 +640,7 @@ void ath9k_enable_mib_counters(struct ath_hw *ah) 
/* Freeze the MIB counters, get the stats and then clear them */

void ath9k_hw_disable_mib_counters(struct ath_hw *ah)

{

	DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disable MIB counters\n");

	DPRINTF(ah, ATH_DBG_ANI, "Disable MIB counters\n");

	REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);

	ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);

	REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
@@ -662,7 +662,7 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, 
	u32 cc = REG_READ(ah, AR_CCCNT);



	if (cycles == 0 || cycles > cc) {

		DPRINTF(ah->ah_sc, ATH_DBG_ANI,

		DPRINTF(ah, ATH_DBG_ANI,

			"cycle counter wrap. ExtBusy = 0\n");

		good = 0;

	} else {
@@ -764,7 +764,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah) 
{

	int i;



	DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Initialize ANI\n");

	DPRINTF(ah, ATH_DBG_ANI, "Initialize ANI\n");



	memset(ah->ani, 0, sizeof(ah->ani));

	for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
@@ -786,10 +786,10 @@ void ath9k_hw_ani_init(struct ath_hw *ah) 
			AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;

	}



	DPRINTF(ah->ah_sc, ATH_DBG_ANI,

	DPRINTF(ah, ATH_DBG_ANI,

		"Setting OfdmErrBase = 0x%08x\n",

		ah->ani[0].ofdmPhyErrBase);

	DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",

	DPRINTF(ah, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",

		ah->ani[0].cckPhyErrBase);



	REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);
@@ -803,7 +803,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah) 


void ath9k_hw_ani_disable(struct ath_hw *ah)

{

	DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disabling ANI\n");

	DPRINTF(ah, ATH_DBG_ANI, "Disabling ANI\n");



	ath9k_hw_disable_mib_counters(ah);

	REG_WRITE(ah, AR_PHY_ERR_1, 0);

drivers/net/wireless/ath/ath9k/beacon.c

+16 −16
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ static int ath_beaconq_config(struct ath_softc *sc) 
	}



	if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) {

		DPRINTF(sc, ATH_DBG_FATAL,

		DPRINTF(ah, ATH_DBG_FATAL,

			"Unable to update h/w beacon queue parameters\n");

		return 0;

	} else {
@@ -172,7 +172,7 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw, 
	if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {

		dev_kfree_skb_any(skb);

		bf->bf_mpdu = NULL;

		DPRINTF(sc, ATH_DBG_FATAL, "dma_mapping_error on beaconing\n");

		DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "dma_mapping_error on beaconing\n");

		return NULL;

	}
@@ -192,7 +192,7 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw, 


	if (skb && cabq_depth) {

		if (sc->nvifs > 1) {

			DPRINTF(sc, ATH_DBG_BEACON,

			DPRINTF(sc->sc_ah, ATH_DBG_BEACON,

				"Flushing previous cabq traffic\n");

			ath_draintxq(sc, cabq, false);

		}
@@ -233,7 +233,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, 
	/* NB: caller is known to have already stopped tx dma */

	ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bf->bf_daddr);

	ath9k_hw_txstart(ah, sc->beacon.beaconq);

	DPRINTF(sc, ATH_DBG_BEACON, "TXDP%u = %llx (%p)\n",

	DPRINTF(ah, ATH_DBG_BEACON, "TXDP%u = %llx (%p)\n",

		sc->beacon.beaconq, ito64(bf->bf_daddr), bf->bf_desc);

}
@@ -309,7 +309,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif) 
	/* NB: the beacon data buffer must be 32-bit aligned. */

	skb = ieee80211_beacon_get(sc->hw, vif);

	if (skb == NULL) {

		DPRINTF(sc, ATH_DBG_BEACON, "cannot get skb\n");

		DPRINTF(sc->sc_ah, ATH_DBG_BEACON, "cannot get skb\n");

		return -ENOMEM;

	}
@@ -333,7 +333,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif) 
		tsfadjust = intval * avp->av_bslot / ATH_BCBUF;

		avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));



		DPRINTF(sc, ATH_DBG_BEACON,

		DPRINTF(sc->sc_ah, ATH_DBG_BEACON,

			"stagger beacons, bslot %d intval %u tsfadjust %llu\n",

			avp->av_bslot, intval, (unsigned long long)tsfadjust);
@@ -349,7 +349,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif) 
	if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {

		dev_kfree_skb_any(skb);

		bf->bf_mpdu = NULL;

		DPRINTF(sc, ATH_DBG_FATAL,

		DPRINTF(sc->sc_ah, ATH_DBG_FATAL,

			"dma_mapping_error on beacon alloc\n");

		return -ENOMEM;

	}
@@ -405,11 +405,11 @@ void ath_beacon_tasklet(unsigned long data) 
		sc->beacon.bmisscnt++;



		if (sc->beacon.bmisscnt < BSTUCK_THRESH) {

			DPRINTF(sc, ATH_DBG_BEACON,

			DPRINTF(sc->sc_ah, ATH_DBG_BEACON,

				"missed %u consecutive beacons\n",

				sc->beacon.bmisscnt);

		} else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {

			DPRINTF(sc, ATH_DBG_BEACON,

			DPRINTF(sc->sc_ah, ATH_DBG_BEACON,

				"beacon is officially stuck\n");

			sc->sc_flags |= SC_OP_TSF_RESET;

			ath_reset(sc, false);
@@ -419,7 +419,7 @@ void ath_beacon_tasklet(unsigned long data) 
	}



	if (sc->beacon.bmisscnt != 0) {

		DPRINTF(sc, ATH_DBG_BEACON,

		DPRINTF(sc->sc_ah, ATH_DBG_BEACON,

			"resume beacon xmit after %u misses\n",

			sc->beacon.bmisscnt);

		sc->beacon.bmisscnt = 0;
@@ -447,7 +447,7 @@ void ath_beacon_tasklet(unsigned long data) 
	vif = sc->beacon.bslot[slot];

	aphy = sc->beacon.bslot_aphy[slot];



	DPRINTF(sc, ATH_DBG_BEACON,

	DPRINTF(sc->sc_ah, ATH_DBG_BEACON,

		"slot %d [tsf %llu tsftu %u intval %u] vif %p\n",

		slot, tsf, tsftu, intval, vif);
@@ -490,7 +490,7 @@ void ath_beacon_tasklet(unsigned long data) 
		 * are still pending on the queue.

		 */

		if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) {

			DPRINTF(sc, ATH_DBG_FATAL,

			DPRINTF(sc->sc_ah, ATH_DBG_FATAL,

				"beacon queue %u did not stop?\n", sc->beacon.beaconq);

		}
@@ -651,8 +651,8 @@ static void ath_beacon_config_sta(struct ath_softc *sc, 
	/* TSF out of range threshold fixed at 1 second */

	bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;



	DPRINTF(sc, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);

	DPRINTF(sc, ATH_DBG_BEACON,

	DPRINTF(sc->sc_ah, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);

	DPRINTF(sc->sc_ah, ATH_DBG_BEACON,

		"bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",

		bs.bs_bmissthreshold, bs.bs_sleepduration,

		bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
@@ -689,7 +689,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc, 
		nexttbtt += intval;

	} while (nexttbtt < tsftu);



	DPRINTF(sc, ATH_DBG_BEACON,

	DPRINTF(sc->sc_ah, ATH_DBG_BEACON,

		"IBSS nexttbtt %u intval %u (%u)\n",

		nexttbtt, intval, conf->beacon_interval);
@@ -759,7 +759,7 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif) 
		ath_beacon_config_sta(sc, cur_conf);

		break;

	default:

		DPRINTF(sc, ATH_DBG_CONFIG,

		DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,

			"Unsupported beaconing mode\n");

		return;

	}

drivers/net/wireless/ath/ath9k/btcoex.c

+4 −4
Original line number Diff line number Diff line
@@ -56,7 +56,7 @@ static void ath_detect_bt_priority(struct ath_softc *sc) 
	if (time_after(jiffies, btinfo->bt_priority_time +

			msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {

		if (btinfo->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {

			DPRINTF(sc, ATH_DBG_BTCOEX,

			DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX,

				"BT priority traffic detected");

			sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;

		} else {
@@ -90,7 +90,7 @@ static void ath_btcoex_bt_stomp(struct ath_softc *sc, 
				      AR_STOMP_NONE_WLAN_WGHT);

		break;

	default:

		DPRINTF(sc, ATH_DBG_BTCOEX, "Invalid Stomptype\n");

		DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX, "Invalid Stomptype\n");

		break;

	}
@@ -142,7 +142,7 @@ static void ath_btcoex_no_stomp_timer(void *arg) 
	struct ath_softc *sc = (struct ath_softc *)arg;

	struct ath_btcoex_info *btinfo = &sc->btcoex_info;



	DPRINTF(sc, ATH_DBG_BTCOEX, "no stomp timer running \n");

	DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX, "no stomp timer running \n");



	spin_lock_bh(&btinfo->btcoex_lock);
@@ -326,7 +326,7 @@ void ath_btcoex_timer_resume(struct ath_softc *sc, 
			     struct ath_btcoex_info *btinfo)

{



	DPRINTF(sc, ATH_DBG_BTCOEX, "Starting btcoex timers");

	DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX, "Starting btcoex timers");



	/* make sure duty cycle timer is also stopped when resuming */

	if (btinfo->hw_timer_enabled)

drivers/net/wireless/ath/ath9k/calib.c

+51 −51
Original line number Diff line number Diff line
@@ -26,7 +26,7 @@ 
static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf)

{

	if (nf > ATH9K_NF_TOO_LOW) {

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"noise floor value detected (%d) is "

			"lower than what we think is a "

			"reasonable value (%d)\n",
@@ -98,7 +98,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah, 


	if (nf & 0x100)

		nf = 0 - ((nf ^ 0x1ff) + 1);

	DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

	DPRINTF(ah, ATH_DBG_CALIBRATE,

		"NF calibrated [ctl] [chain 0] is %d\n", nf);

	nfarray[0] = nf;
@@ -112,7 +112,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah, 


		if (nf & 0x100)

			nf = 0 - ((nf ^ 0x1ff) + 1);

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

				"NF calibrated [ctl] [chain 1] is %d\n", nf);

		nfarray[1] = nf;
@@ -121,7 +121,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah, 
					AR_PHY_CH2_MINCCA_PWR);

			if (nf & 0x100)

				nf = 0 - ((nf ^ 0x1ff) + 1);

			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

			DPRINTF(ah, ATH_DBG_CALIBRATE,

				"NF calibrated [ctl] [chain 2] is %d\n", nf);

			nfarray[2] = nf;

		}
@@ -136,7 +136,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah, 


	if (nf & 0x100)

		nf = 0 - ((nf ^ 0x1ff) + 1);

	DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

	DPRINTF(ah, ATH_DBG_CALIBRATE,

		"NF calibrated [ext] [chain 0] is %d\n", nf);

	nfarray[3] = nf;
@@ -150,7 +150,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah, 


		if (nf & 0x100)

			nf = 0 - ((nf ^ 0x1ff) + 1);

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

				"NF calibrated [ext] [chain 1] is %d\n", nf);

		nfarray[4] = nf;
@@ -159,7 +159,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah, 
					AR_PHY_CH2_EXT_MINCCA_PWR);

			if (nf & 0x100)

				nf = 0 - ((nf ^ 0x1ff) + 1);

			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

			DPRINTF(ah, ATH_DBG_CALIBRATE,

				"NF calibrated [ext] [chain 2] is %d\n", nf);

			nfarray[5] = nf;

		}
@@ -195,22 +195,22 @@ static void ath9k_hw_setup_calibration(struct ath_hw *ah, 
	switch (currCal->calData->calType) {

	case IQ_MISMATCH_CAL:

		REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"starting IQ Mismatch Calibration\n");

		break;

	case ADC_GAIN_CAL:

		REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"starting ADC Gain Calibration\n");

		break;

	case ADC_DC_CAL:

		REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"starting ADC DC Calibration\n");

		break;

	case ADC_DC_INIT_CAL:

		REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"starting Init ADC DC Calibration\n");

		break;

	}
@@ -304,7 +304,7 @@ static void ath9k_hw_iqcal_collect(struct ath_hw *ah) 
			REG_READ(ah, AR_PHY_CAL_MEAS_1(i));

		ah->totalIqCorrMeas[i] +=

			(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",

			ah->cal_samples, i, ah->totalPowerMeasI[i],

			ah->totalPowerMeasQ[i],
@@ -326,7 +326,7 @@ static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah) 
		ah->totalAdcQEvenPhase[i] +=

			REG_READ(ah, AR_PHY_CAL_MEAS_3(i));



		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"%d: Chn %d oddi=0x%08x; eveni=0x%08x; "

			"oddq=0x%08x; evenq=0x%08x;\n",

			ah->cal_samples, i,
@@ -351,7 +351,7 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah) 
		ah->totalAdcDcOffsetQEvenPhase[i] +=

			(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));



		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"%d: Chn %d oddi=0x%08x; eveni=0x%08x; "

			"oddq=0x%08x; evenq=0x%08x;\n",

			ah->cal_samples, i,
@@ -374,11 +374,11 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) 
		powerMeasQ = ah->totalPowerMeasQ[i];

		iqCorrMeas = ah->totalIqCorrMeas[i];



		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"Starting IQ Cal and Correction for Chain %d\n",

			i);



		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"Orignal: Chn %diq_corr_meas = 0x%08x\n",

			i, ah->totalIqCorrMeas[i]);
@@ -389,11 +389,11 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) 
			iqCorrNeg = 1;

		}



		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",

		DPRINTF(ah, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",

			iqCorrNeg);



		iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
@@ -402,13 +402,13 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) 
		if (powerMeasQ != 0) {

			iCoff = iqCorrMeas / iCoffDenom;

			qCoff = powerMeasI / qCoffDenom - 64;

			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

			DPRINTF(ah, ATH_DBG_CALIBRATE,

				"Chn %d iCoff = 0x%08x\n", i, iCoff);

			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

			DPRINTF(ah, ATH_DBG_CALIBRATE,

				"Chn %d qCoff = 0x%08x\n", i, qCoff);



			iCoff = iCoff & 0x3f;

			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

			DPRINTF(ah, ATH_DBG_CALIBRATE,

				"New: Chn %d iCoff = 0x%08x\n", i, iCoff);

			if (iqCorrNeg == 0x0)

				iCoff = 0x40 - iCoff;
@@ -418,7 +418,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) 
			else if (qCoff <= -16)

				qCoff = 16;



			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

			DPRINTF(ah, ATH_DBG_CALIBRATE,

				"Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",

				i, iCoff, qCoff);
@@ -428,7 +428,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) 
			REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),

				      AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,

				      qCoff);

			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

			DPRINTF(ah, ATH_DBG_CALIBRATE,

				"IQ Cal and Correction done for Chain %d\n",

				i);

		}
@@ -449,19 +449,19 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) 
		qOddMeasOffset = ah->totalAdcQOddPhase[i];

		qEvenMeasOffset = ah->totalAdcQEvenPhase[i];



		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"Starting ADC Gain Cal for Chain %d\n", i);



		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_odd_i = 0x%08x\n", i,

			iOddMeasOffset);

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_even_i = 0x%08x\n", i,

			iEvenMeasOffset);

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_odd_q = 0x%08x\n", i,

			qOddMeasOffset);

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_even_q = 0x%08x\n", i,

			qEvenMeasOffset);
@@ -473,10 +473,10 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) 
				((qOddMeasOffset * 32) /

				 qEvenMeasOffset) & 0x3f;



			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

			DPRINTF(ah, ATH_DBG_CALIBRATE,

				"Chn %d gain_mismatch_i = 0x%08x\n", i,

				iGainMismatch);

			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

			DPRINTF(ah, ATH_DBG_CALIBRATE,

				"Chn %d gain_mismatch_q = 0x%08x\n", i,

				qGainMismatch);
@@ -485,7 +485,7 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) 
			val |= (qGainMismatch) | (iGainMismatch << 6);

			REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);



			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

			DPRINTF(ah, ATH_DBG_CALIBRATE,

				"ADC Gain Cal done for Chain %d\n", i);

		}

	}
@@ -510,19 +510,19 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) 
		qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];

		qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];



		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"Starting ADC DC Offset Cal for Chain %d\n", i);



		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_odd_i = %d\n", i,

			iOddMeasOffset);

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_even_i = %d\n", i,

			iEvenMeasOffset);

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_odd_q = %d\n", i,

			qOddMeasOffset);

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"Chn %d pwr_meas_even_q = %d\n", i,

			qEvenMeasOffset);
@@ -531,10 +531,10 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) 
		qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /

			       numSamples) & 0x1ff;



		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"Chn %d dc_offset_mismatch_i = 0x%08x\n", i,

			iDcMismatch);

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"Chn %d dc_offset_mismatch_q = 0x%08x\n", i,

			qDcMismatch);
@@ -543,7 +543,7 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) 
		val |= (qDcMismatch << 12) | (iDcMismatch << 21);

		REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);



		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"ADC DC Offset Cal done for Chain %d\n", i);

	}
@@ -568,7 +568,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah) 
		return true;



	if (currCal->calState != CAL_DONE) {

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"Calibration state incorrect, %d\n",

			currCal->calState);

		return true;
@@ -577,7 +577,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah) 
	if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType))

		return true;



	DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

	DPRINTF(ah, ATH_DBG_CALIBRATE,

		"Resetting Cal %d state for channel %u\n",

		currCal->calData->calType, conf->channel->center_freq);
@@ -672,7 +672,7 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah, 


	chan->channelFlags &= (~CHANNEL_CW_INT);

	if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

		DPRINTF(ah, ATH_DBG_CALIBRATE,

			"NF did not complete in calibration window\n");

		nf = 0;

		chan->rawNoiseFloor = nf;
@@ -682,7 +682,7 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah, 
		nf = nfarray[0];

		if (getNoiseFloorThresh(ah, c->band, &nfThresh)

		    && nf > nfThresh) {

			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

			DPRINTF(ah, ATH_DBG_CALIBRATE,

				"noise floor failed detected; "

				"detected %d, threshold %d\n",

				nf, nfThresh);
@@ -889,7 +889,7 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset) 
		{ 0x7838, 0 },

	};



	DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Running PA Calibration\n");

	DPRINTF(ah, ATH_DBG_CALIBRATE, "Running PA Calibration\n");



	/* PA CAL is not needed for high power solution */

	if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
@@ -1049,7 +1049,7 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan) 
		REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);

		if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,

				  AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {

			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset "

			DPRINTF(ah, ATH_DBG_CALIBRATE, "offset "

				"calibration failed to complete in "

				"1ms; noisy ??\n");

			return false;
@@ -1064,7 +1064,7 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan) 
	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);

	if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,

			  0, AH_WAIT_TIMEOUT)) {

		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset calibration "

		DPRINTF(ah, ATH_DBG_CALIBRATE, "offset calibration "

				"failed to complete in 1ms; noisy ??\n");

		return false;

	}
@@ -1098,7 +1098,7 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) 
		/* Poll for offset calibration complete */

		if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,

				   0, AH_WAIT_TIMEOUT)) {

			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

			DPRINTF(ah, ATH_DBG_CALIBRATE,

				"offset calibration failed to complete in 1ms; "

				"noisy environment?\n");

			return false;
@@ -1128,19 +1128,19 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) 
		if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {

			INIT_CAL(&ah->adcgain_caldata);

			INSERT_CAL(ah, &ah->adcgain_caldata);

			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

			DPRINTF(ah, ATH_DBG_CALIBRATE,

				"enabling ADC Gain Calibration.\n");

		}

		if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {

			INIT_CAL(&ah->adcdc_caldata);

			INSERT_CAL(ah, &ah->adcdc_caldata);

			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

			DPRINTF(ah, ATH_DBG_CALIBRATE,

				"enabling ADC DC Calibration.\n");

		}

		if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {

			INIT_CAL(&ah->iq_caldata);

			INSERT_CAL(ah, &ah->iq_caldata);

			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,

			DPRINTF(ah, ATH_DBG_CALIBRATE,

				"enabling IQ Calibration.\n");

		}