Commit 4f76da23 authored by Chris Park's avatar Chris Park Committed by Alex Deucher
Browse files

drm/amd/display: Correct I2C register offset 



[Why]
I2C register name starts with 1, unlike other registers that start with
0. This creates a problem with the new register macro refactoring when
I2C HW objects are created in an array.

[How]
Correct I2C register offset by making a new macro to account for array
offset.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarPavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: default avatarChris Park <chris.park@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 17529ea2

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

+8 −1
Original line number Diff line number Diff line
@@ -152,6 +152,13 @@ enum dcn32_clk_src_array_id { 
	REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

		reg ## block ## id ## _ ## reg_name



#define SR_ARR_I2C(reg_name, id) \

	REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name



#define SRI_ARR_I2C(reg_name, block, id)\

	REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

		reg ## block ## id ## _ ## reg_name



#define SRI_ARR_ALPHABET(reg_name, block, index, id)\

	REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

		reg ## block ## id ## _ ## reg_name
@@ -792,7 +799,7 @@ static struct dce_aux *dcn32_aux_engine_create( 
#define i2c_inst_regs_init(id)\

	I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)



static struct dce_i2c_registers i2c_hw_regs[6];

static struct dce_i2c_registers i2c_hw_regs[5];



static const struct dce_i2c_shift i2c_shifts = {

		I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h

+9 −8
Original line number Diff line number Diff line
@@ -1175,18 +1175,19 @@ void dcn32_determine_det_override(struct dc_state *context, display_e2e_pipe_par 


#define I2C_HW_ENGINE_COMMON_REG_LIST_RI(id)                                   \

  ( \

  SRI_ARR(SETUP, DC_I2C_DDC, id), SRI_ARR(SPEED, DC_I2C_DDC, id),              \

      SRI_ARR(HW_STATUS, DC_I2C_DDC, id), SR_ARR(DC_I2C_ARBITRATION, id),      \

      SR_ARR(DC_I2C_CONTROL, id), SR_ARR(DC_I2C_SW_STATUS, id),                \

      SR_ARR(DC_I2C_TRANSACTION0, id), SR_ARR(DC_I2C_TRANSACTION1, id),        \

      SR_ARR(DC_I2C_TRANSACTION2, id), SR_ARR(DC_I2C_TRANSACTION3, id),        \

      SR_ARR(DC_I2C_DATA, id), SR_ARR(MICROSECOND_TIME_BASE_DIV, id)           \

      SRI_ARR_I2C(SETUP, DC_I2C_DDC, id), SRI_ARR_I2C(SPEED, DC_I2C_DDC, id),  \

      SRI_ARR_I2C(HW_STATUS, DC_I2C_DDC, id),                                  \

      SR_ARR_I2C(DC_I2C_ARBITRATION, id),                                      \

      SR_ARR_I2C(DC_I2C_CONTROL, id), SR_ARR_I2C(DC_I2C_SW_STATUS, id),        \

      SR_ARR_I2C(DC_I2C_TRANSACTION0, id), SR_ARR_I2C(DC_I2C_TRANSACTION1, id),\

      SR_ARR_I2C(DC_I2C_TRANSACTION2, id), SR_ARR_I2C(DC_I2C_TRANSACTION3, id),\

      SR_ARR_I2C(DC_I2C_DATA, id), SR_ARR_I2C(MICROSECOND_TIME_BASE_DIV, id)          \

  )



#define I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)                             \

  ( \

  I2C_HW_ENGINE_COMMON_REG_LIST_RI(id), SR_ARR(DIO_MEM_PWR_CTRL, id),          \

      SR_ARR(DIO_MEM_PWR_STATUS, id)                                           \

      I2C_HW_ENGINE_COMMON_REG_LIST_RI(id), SR_ARR_I2C(DIO_MEM_PWR_CTRL, id),  \

      SR_ARR_I2C(DIO_MEM_PWR_STATUS, id)                                           \

  )



#endif /* _DCN32_RESOURCE_H_ */

drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c

+8 −1
Original line number Diff line number Diff line
@@ -159,6 +159,13 @@ enum dcn321_clk_src_array_id { 
	REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

		reg ## block ## id ## _ ## reg_name



#define SR_ARR_I2C(reg_name, id) \

	REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name



#define SRI_ARR_I2C(reg_name, block, id)\

	REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

		reg ## block ## id ## _ ## reg_name



#define SRI_ARR_ALPHABET(reg_name, block, index, id)\

	REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

		reg ## block ## id ## _ ## reg_name
@@ -796,7 +803,7 @@ static struct dce_aux *dcn321_aux_engine_create( 
#define i2c_inst_regs_init(id)\

	I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)



static struct dce_i2c_registers i2c_hw_regs[6];

static struct dce_i2c_registers i2c_hw_regs[5];



static const struct dce_i2c_shift i2c_shifts = {

		I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)