Commit 4fb0b930 authored by Yunus Bas's avatar Yunus Bas Committed by Shawn Guo
Browse files

ARM: dts: imx6: phytec: Add gpio pinctrl for i2c bus recovery 



Make use of the i2c bus recovery feature and enable it on PHYTEC
phyCORE-based modules and boards.

Signed-off-by: default avatarYunus Bas <y.bas@phytec.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 0fa8bc5d

arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi

+25 −5
Original line number Diff line number Diff line
@@ -145,8 +145,11 @@ &hdmi { 
};



&i2c1 {

	pinctrl-names = "default";

	pinctrl-names = "default", "gpio";

	pinctrl-0 = <&pinctrl_i2c1>;

	pinctrl-1 = <&pinctrl_i2c1_gpio>;

	scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	clock-frequency = <400000>;

	status = "disabled";
@@ -185,8 +188,11 @@ i2c_rtc: rtc@68 { 
};



&i2c2 {

	pinctrl-names = "default";

	pinctrl-names = "default", "gpio";

	pinctrl-0 = <&pinctrl_i2c2>;

	pinctrl-1 = <&pinctrl_i2c2_gpio>;

	scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	clock-frequency = <100000>;

	status = "disabled";

};
@@ -300,6 +306,20 @@ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 
		>;

	};



	pinctrl_i2c1: i2c1grp {

		fsl,pins = <

			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1

			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1

		>;

	};



	pinctrl_i2c1_gpio: i2c1gpiogrp {

		fsl,pins = <

			MX6QDL_PAD_EIM_D21__GPIO3_IO21		0x4001b8b1

			MX6QDL_PAD_EIM_D28__GPIO3_IO28		0x4001b8b1

		>;

	};



	pinctrl_i2c2: i2c2grp {

		fsl,pins = <

			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
@@ -307,10 +327,10 @@ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 
		>;

	};



	pinctrl_i2c1: i2c1grp {

	pinctrl_i2c2_gpio: i2c2gpiogrp {

		fsl,pins = <

			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1

			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1

			MX6QDL_PAD_KEY_ROW3__GPIO4_IO13		0x4001b8b1

			MX6QDL_PAD_KEY_COL3__GPIO4_IO12		0x4001b8b1

		>;

	};

arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi

+11 −1
Original line number Diff line number Diff line
@@ -78,8 +78,11 @@ &gpmi { 
};



&i2c3 {

	pinctrl-names = "default";

	pinctrl-names = "default", "gpio";

	pinctrl-0 = <&pinctrl_i2c3>;

	pinctrl-1 = <&pinctrl_i2c3_gpio>;

	scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	clock-frequency = <400000>;

	status = "okay";
@@ -259,6 +262,13 @@ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 
		>;

	};



	pinctrl_i2c3_gpio: i2c3gpiogrp {

		fsl,pins = <

			MX6QDL_PAD_GPIO_6__GPIO1_IO06	0x4001b8b1

			MX6QDL_PAD_GPIO_5__GPIO1_IO05	0x4001b8b1

		>;

	};



	pinctrl_ecspi1: ecspi1grp {

		fsl,pins = <

			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1

arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi

+11 −1
Original line number Diff line number Diff line
@@ -68,8 +68,11 @@ &gpmi { 
};



&i2c1 {

	pinctrl-names = "default";

	pinctrl-names = "default", "gpio";

	pinctrl-0 = <&pinctrl_i2c1>;

	pinctrl-1 = <&pinctrl_i2c1_gpio>;

	scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	clock-frequency = <100000>;

	status = "okay";
@@ -147,6 +150,13 @@ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 
		>;

	};



	pinctrl_i2c1_gpio: i2cgpiogrp {

		fsl,pins = <

			MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28	0x4001b8b0

			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29	0x4001b8b0

		>;

	};



	pinctrl_uart1: uart1grp {

		fsl,pins = <

			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1