Loading drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c +1 −6 Original line number Diff line number Diff line Loading @@ -1424,12 +1424,7 @@ gk104_ram_init(struct nvkm_ram *ram) for (i = 0; i < cnt; i++, data += 4) { if (i != save >> 4) { nvkm_mask(device, 0x10f65c, 0x000000f0, i << 4); nvbios_exec(&(struct nvbios_init) { .subdev = subdev, .bios = bios, .offset = nvbios_rd32(bios, data), .execute = 1, }); nvbios_init(subdev, nvbios_rd32(bios, data)); } } nvkm_mask(device, 0x10f65c, 0x000000f0, save); Loading drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.c +1 −6 Original line number Diff line number Diff line Loading @@ -59,12 +59,7 @@ gp100_ram_init(struct nvkm_ram *ram) for (i = 0; i < cnt; i++, data += 4) { if (i != save >> 4) { nvkm_mask(device, 0x9a065c, 0x000000f0, i << 4); nvbios_exec(&(struct nvbios_init) { .subdev = subdev, .bios = bios, .offset = nvbios_rd32(bios, data), .execute = 1, }); nvbios_init(subdev, nvbios_rd32(bios, data)); } } nvkm_mask(device, 0x9a065c, 0x000000f0, save); Loading drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c +2 −10 Original line number Diff line number Diff line Loading @@ -150,16 +150,8 @@ nv40_ram_prog(struct nvkm_ram *base) udelay(100); /* execute memory reset script from vbios */ if (!bit_entry(bios, 'M', &M)) { struct nvbios_init init = { .subdev = subdev, .bios = bios, .offset = nvbios_rd16(bios, M.offset + 0x00), .execute = 1, }; nvbios_exec(&init); } if (!bit_entry(bios, 'M', &M)) nvbios_init(subdev, nvbios_rd16(bios, M.offset + 0x00)); /* make sure we're in vblank (hopefully the same one as before), and * then re-enable crtc memory access Loading Loading
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c +1 −6 Original line number Diff line number Diff line Loading @@ -1424,12 +1424,7 @@ gk104_ram_init(struct nvkm_ram *ram) for (i = 0; i < cnt; i++, data += 4) { if (i != save >> 4) { nvkm_mask(device, 0x10f65c, 0x000000f0, i << 4); nvbios_exec(&(struct nvbios_init) { .subdev = subdev, .bios = bios, .offset = nvbios_rd32(bios, data), .execute = 1, }); nvbios_init(subdev, nvbios_rd32(bios, data)); } } nvkm_mask(device, 0x10f65c, 0x000000f0, save); Loading
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.c +1 −6 Original line number Diff line number Diff line Loading @@ -59,12 +59,7 @@ gp100_ram_init(struct nvkm_ram *ram) for (i = 0; i < cnt; i++, data += 4) { if (i != save >> 4) { nvkm_mask(device, 0x9a065c, 0x000000f0, i << 4); nvbios_exec(&(struct nvbios_init) { .subdev = subdev, .bios = bios, .offset = nvbios_rd32(bios, data), .execute = 1, }); nvbios_init(subdev, nvbios_rd32(bios, data)); } } nvkm_mask(device, 0x9a065c, 0x000000f0, save); Loading
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c +2 −10 Original line number Diff line number Diff line Loading @@ -150,16 +150,8 @@ nv40_ram_prog(struct nvkm_ram *base) udelay(100); /* execute memory reset script from vbios */ if (!bit_entry(bios, 'M', &M)) { struct nvbios_init init = { .subdev = subdev, .bios = bios, .offset = nvbios_rd16(bios, M.offset + 0x00), .execute = 1, }; nvbios_exec(&init); } if (!bit_entry(bios, 'M', &M)) nvbios_init(subdev, nvbios_rd16(bios, M.offset + 0x00)); /* make sure we're in vblank (hopefully the same one as before), and * then re-enable crtc memory access Loading