Commit 5038ffea authored by Russell King (Oracle)'s avatar Russell King (Oracle) Committed by David S. Miller
Browse files

net: mvpp2: use phylink_generic_validate() 



Convert mvpp2 to use phylink_generic_validate() for the bulk of its
validate() implementation. This network adapter has a restriction
that for 802.3z links, autonegotiation must be enabled.

Signed-off-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 02a0988b

drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c

+9 −49
Original line number Diff line number Diff line
@@ -6260,9 +6260,6 @@ static void mvpp2_phylink_validate(struct phylink_config *config, 
				   unsigned long *supported,

				   struct phylink_link_state *state)

{

	struct mvpp2_port *port = mvpp2_phylink_to_port(config);

	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };



	/* When in 802.3z mode, we must have AN enabled:

	 * Bit 2 Field InBandAnEn In-band Auto-Negotiation enable. ...

	 * When <PortType> = 1 (1000BASE-X) this field must be set to 1.
@@ -6271,52 +6268,7 @@ static void mvpp2_phylink_validate(struct phylink_config *config, 
	    !phylink_test(state->advertising, Autoneg))

		goto empty_set;



	phylink_set(mask, Autoneg);

	phylink_set_port_modes(mask);



	if (port->priv->global_tx_fc) {

		phylink_set(mask, Pause);

		phylink_set(mask, Asym_Pause);

	}



	switch (state->interface) {

	case PHY_INTERFACE_MODE_10GBASER:

	case PHY_INTERFACE_MODE_XAUI:

		if (mvpp2_port_supports_xlg(port)) {

			phylink_set_10g_modes(mask);

			phylink_set(mask, 10000baseKR_Full);

		}

		break;



	case PHY_INTERFACE_MODE_RGMII:

	case PHY_INTERFACE_MODE_RGMII_ID:

	case PHY_INTERFACE_MODE_RGMII_RXID:

	case PHY_INTERFACE_MODE_RGMII_TXID:

	case PHY_INTERFACE_MODE_SGMII:

		phylink_set(mask, 10baseT_Half);

		phylink_set(mask, 10baseT_Full);

		phylink_set(mask, 100baseT_Half);

		phylink_set(mask, 100baseT_Full);

		phylink_set(mask, 1000baseT_Full);

		phylink_set(mask, 1000baseX_Full);

		break;



	case PHY_INTERFACE_MODE_1000BASEX:

		phylink_set(mask, 1000baseT_Full);

		phylink_set(mask, 1000baseX_Full);

		break;



	case PHY_INTERFACE_MODE_2500BASEX:

		phylink_set(mask, 2500baseT_Full);

		phylink_set(mask, 2500baseX_Full);

		break;



	default:

		goto empty_set;

	}



	linkmode_and(supported, supported, mask);

	linkmode_and(state->advertising, state->advertising, mask);

	phylink_generic_validate(config, supported, state);

	return;



empty_set:
@@ -6911,12 +6863,20 @@ static int mvpp2_port_probe(struct platform_device *pdev, 
	if (!mvpp2_use_acpi_compat_mode(port_fwnode)) {

		port->phylink_config.dev = &dev->dev;

		port->phylink_config.type = PHYLINK_NETDEV;

		port->phylink_config.mac_capabilities =

			MAC_2500FD | MAC_1000FD | MAC_100 | MAC_10;



		if (port->priv->global_tx_fc)

			port->phylink_config.mac_capabilities |=

				MAC_SYM_PAUSE | MAC_ASYM_PAUSE;



		if (mvpp2_port_supports_xlg(port)) {

			__set_bit(PHY_INTERFACE_MODE_10GBASER,

				  port->phylink_config.supported_interfaces);

			__set_bit(PHY_INTERFACE_MODE_XAUI,

				  port->phylink_config.supported_interfaces);

			port->phylink_config.mac_capabilities |=

				MAC_10000FD;

		}



		if (mvpp2_port_supports_rgmii(port))