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Unverified Commit 507308b8 authored by Yash Shah's avatar Yash Shah Committed by Palmer Dabbelt
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RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740



SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540.
Update the L2 cache controller driver to support this additional
interrupt in case of FU740-C000 chip.

Signed-off-by: default avatarYash Shah <yash.shah@sifive.com>
Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
parent af951c3a
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