Commit 5217811e authored by Kevin Wang's avatar Kevin Wang Committed by Alex Deucher
Browse files

drm/amdgpu: add gc powerbrake support (v2) 



add GC power brake feature support for Aldebaran.

v2: squash in fixes (Alex)

Signed-off-by: default avatarKevin Wang <kevin1.wang@amd.com>
Reviewed-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b3ecf36b

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+3 −0
Original line number Diff line number Diff line
@@ -3951,6 +3951,9 @@ static int gfx_v9_0_hw_init(void *handle) 
	if (r)

		return r;



	if (adev->asic_type == CHIP_ALDEBARAN)

		gfx_v9_4_2_set_power_brake_sequence(adev);



	return r;

}

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

+26 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 


#include "gc/gc_9_4_2_offset.h"

#include "gc/gc_9_4_2_sh_mask.h"

#include "gfx_v9_0.h"



static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde_die_0[] = {

	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_0, 0x3fffffff, 0x141dc920),
@@ -102,3 +103,28 @@ void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev, 
	soc15_grbm_select(adev, 0, 0, 0, 0);

	mutex_unlock(&adev->srbm_mutex);

}



void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev)

{

	u32 tmp;



	gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);



	tmp = 0;

	tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL, PATTERN_MODE, 1);

	WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL, tmp);



	tmp = 0;

	tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL1, PWRBRK_STALL_EN, 1);

	WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL1, tmp);



	WREG32_SOC15(GC, 0, regDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);

	tmp = 0;

	tmp = REG_SET_FIELD(tmp, DIDT_SQ_THROTTLE_CTRL, PWRBRK_STALL_EN, 1);

	WREG32_SOC15(GC, 0, regDIDT_IND_DATA, tmp);



	WREG32_SOC15(GC, 0, regGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);

	tmp = 0;

	tmp = REG_SET_FIELD(tmp, PWRBRK_STALL_PATTERN_CTRL, PWRBRK_END_STEP, 0x12);

	WREG32_SOC15(GC, 0, regGC_CAC_IND_DATA, tmp);

}

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h

+1 −0
Original line number Diff line number Diff line
@@ -28,4 +28,5 @@ void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev, 
				uint32_t first_vmid, uint32_t last_vmid);

void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev,

				      uint32_t die_id);

void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev);

#endif /* __GFX_V9_4_2_H__ */