Commit 5474405f authored by Bartlomiej Zolnierkiewicz's avatar Bartlomiej Zolnierkiewicz Committed by Greg Kroah-Hartman
Browse files

Staging: rtl8187se: remove CONFIG_RTL818x_S ifdefs 



CONFIG_RTL818x_S is defined in drivers/staging/rtl8187se/r8180_hw.h.

Signed-off-by: default avatarBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 9a5aabff

drivers/staging/rtl8187se/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -5,7 +5,6 @@ 
#EXTRA_CFLAGS += -O2

#CC            = gcc

#CFLAGS += -DCONFIG_RTL8185B

#CFLAGS += -DCONFIG_RTL818x_S



#added for EeePC testing

EXTRA_CFLAGS += -DENABLE_IPS

drivers/staging/rtl8187se/r8180_core.c

+0 −40
Original line number Diff line number Diff line
@@ -2479,9 +2479,7 @@ void rtl8180_rx(struct net_device *dev) 
		}else {

			padding = 0;

		}

#ifdef CONFIG_RTL818X_S

               padding = 0;

#endif

#endif

		priv->rx_prevlen+=len;
@@ -3862,13 +3860,11 @@ void watch_dog_adaptive(unsigned long data) 
	}

#endif



#ifdef CONFIG_RTL818X_S

	// Tx Power Tracking on 87SE.

#ifdef TX_TRACK

	//if( priv->bTxPowerTrack )	//lzm mod 080826

	if( CheckTxPwrTracking((struct net_device *)data));

		TxPwrTracking87SE((struct net_device *)data);

#endif

#endif



	// Perform DIG immediately.
@@ -4024,11 +4020,7 @@ short rtl8180_init(struct net_device *dev) 
	 */



#ifdef CONFIG_RTL8185B

#ifdef CONFIG_RTL818X_S

	priv->RegThreeWireMode = HW_THREE_WIRE_SI;

#else

        priv->RegThreeWireMode = SW_THREE_WIRE;

#endif

#endif



//Add for RF power on power off by lizhaoming 080512
@@ -4269,10 +4261,6 @@ short rtl8180_init(struct net_device *dev) 
									(0 ? TCR_SAT : 0);	// FALSE: HW provies PLCP length and LENGEXT, TURE: SW proiveds them



	priv->ReceiveConfig	=

#ifdef CONFIG_RTL818X_S

#else

                                                        priv->CSMethod |

#endif

//								RCR_ENMARP |

								RCR_AMF | RCR_ADF |				//accept management/data

								RCR_ACF |						//accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko.
@@ -4300,17 +4288,10 @@ short rtl8180_init(struct net_device *dev) 
	switch (hw_version){

#ifdef CONFIG_RTL8185B

		case HW_VERID_R8185B_B:

#ifdef CONFIG_RTL818X_S

                        priv->card_8185 = VERSION_8187S_C;

		        DMESG("MAC controller is a RTL8187SE b/g");

			priv->phy_ver = 2;

			break;

#else

			DMESG("MAC controller is a RTL8185B b/g");

			priv->card_8185 = 3;

			priv->phy_ver = 2;

			break;

#endif

#endif

		case HW_VERID_R8185_ABC:

			DMESG("MAC controller is a RTL8185 b/g");
@@ -4350,24 +4331,9 @@ short rtl8180_init(struct net_device *dev) 
	priv->card_8185_Bversion = 0;



#ifdef CONFIG_RTL8185B

#ifdef CONFIG_RTL818X_S

	// just for sync 85

	priv->card_type = PCI;

        DMESG("This is a PCI NIC");

#else

	config3 = read_nic_byte(dev, CONFIG3);

	if(config3 & 0x8){

		priv->card_type = CARDBUS;

		DMESG("This is a CARDBUS NIC");

	}

	else if( config3 & 0x4){

		priv->card_type = MINIPCI;

		DMESG("This is a MINI-PCI NIC");

	}else{

		priv->card_type = PCI;

		DMESG("This is a PCI NIC");

	}

#endif

#endif

	priv->enable_gpio0 = 0;
@@ -4375,7 +4341,6 @@ short rtl8180_init(struct net_device *dev) 
#ifdef CONFIG_RTL8185B

	usValue = eprom_read(dev, EEPROM_SW_REVD_OFFSET);

	DMESG("usValue is 0x%x\n",usValue);

#ifdef CONFIG_RTL818X_S

	//3Read AntennaDiversity

	// SW Antenna Diversity.

	if(	(usValue & EEPROM_SW_AD_MASK) != EEPROM_SW_AD_ENABLE )
@@ -4427,7 +4392,6 @@ short rtl8180_init(struct net_device *dev) 
	}

	//printk("bDefaultAntenna1 = %d\n", priv->bDefaultAntenna1);

#endif

#endif

//by amy for antenna

	/* rtl8185 can calc plcp len in HW.*/

	priv->hw_plcp_len = 1;
@@ -4537,13 +4501,9 @@ DMESG output to andreamrl@tiscali.it THANKS"); 
	}



#ifdef CONFIG_RTL8185B

#ifdef CONFIG_RTL818X_S

	priv->rf_chip = RF_ZEBRA4;

	priv->rf_sleep = rtl8225z4_rf_sleep;

	priv->rf_wakeup = rtl8225z4_rf_wakeup;

#else

        priv->rf_chip = RF_ZEBRA2;

#endif

	//DMESG("Card reports RF frontend Realtek 8225z2");

	//DMESGW("This driver has EXPERIMENTAL support for this chipset.");

	//DMESGW("use it with care and at your own risk and");

drivers/staging/rtl8187se/r8180_dm.c

+0 −24
Original line number Diff line number Diff line
@@ -517,7 +517,6 @@ MgntIsCckRate( 


        return bReturn;

}

#ifdef CONFIG_RTL818X_S

//

//	Description:

//		Tx Power tracking mechanism routine on 87SE.
@@ -1233,7 +1232,6 @@ StaRateAdaptive87SE( 
	priv->LastTxThroughput = TxThroughput;

	priv->ieee80211->rate = priv->CurrentOperaRate * 5;

}

#endif



void rtl8180_rate_adapter(struct work_struct * work)

{
@@ -1259,10 +1257,8 @@ void timer_rate_adaptive(unsigned long data) 
			(priv->ForcedDataRate == 0) )

	{

//	DMESG("timer_rate_adaptive():schedule rate_adapter_wq\n");

#ifdef CONFIG_RTL818X_S

		queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->rate_adapter_wq);

//		StaRateAdaptive87SE((struct net_device *)data);

#endif

	}

	priv->rateadapter_timer.expires = jiffies + MSECS(priv->RateAdaptivePeriod);

	add_timer(&priv->rateadapter_timer);
@@ -1320,20 +1316,12 @@ SetAntenna8185( 
		case RF_ZEBRA2:

		case RF_ZEBRA4:

#ifdef CONFIG_RTL8185B

#ifdef CONFIG_RTL818X_S

			// Mac register, main antenna

			write_nic_byte(dev, ANTSEL, 0x03);

			//base band

			write_phy_cck(dev,0x11, 0x9b); // Config CCK RX antenna.

			write_phy_ofdm(dev, 0x0d, 0x5c); // Config OFDM RX antenna.



#else

			// Mac register, main antenna

			write_nic_byte(dev, ANTSEL, 0x03);

			//base band

			write_phy_cck(dev, 0x10, 0x9b); // Config CCK RX antenna.

			write_phy_ofdm(dev, 0x0d, 0x5c); // Config OFDM RX antenna.

#endif

#endif



			bAntennaSwitched = true;
@@ -1351,19 +1339,11 @@ SetAntenna8185( 
		case RF_ZEBRA2:

		case RF_ZEBRA4:

#ifdef CONFIG_RTL8185B

#ifdef CONFIG_RTL818X_S

			// Mac register, aux antenna

			write_nic_byte(dev, ANTSEL, 0x00);

			//base band

			write_phy_cck(dev, 0x11, 0xbb); // Config CCK RX antenna.

			write_phy_ofdm(dev, 0x0d, 0x54); // Config OFDM RX antenna.

#else

			// Mac register, aux antenna

			write_nic_byte(dev, ANTSEL, 0x00);

			//base band

			write_phy_cck(dev, 0x10, 0xbb); // Config CCK RX antenna.

			write_phy_ofdm(dev, 0x0d, 0x54); // Config OFDM RX antenna.

#endif

#endif



			bAntennaSwitched = true;
@@ -1406,11 +1386,9 @@ SwitchAntenna( 
	{

#if 0//lzm del 080826

//by amy 080312

#ifdef CONFIG_RTL818X_S

		if(priv->bSwAntennaDiverity)

			bResult = SetAntennaConfig87SE(dev, 1, true);

		else

#endif

#endif

			bResult = SetAntenna8185(dev, 1);

//by amy 080312
@@ -1421,11 +1399,9 @@ SwitchAntenna( 
	{

#if 0//lzm del 080826

//by amy 080312

#ifdef CONFIG_RTL818X_S

		if(priv->bSwAntennaDiverity)

			bResult = SetAntennaConfig87SE(dev, 0, true);

		else

#endif

#endif

			bResult = SetAntenna8185(dev, 0);

//by amy 080312

drivers/staging/rtl8187se/r8180_hw.h

+0 −18
Original line number Diff line number Diff line
@@ -21,7 +21,6 @@ 
#define R8180_HW



#define CONFIG_RTL8185B  //support for rtl8185B, xiong-2006-11-15

#define CONFIG_RTL818X_S



#define BIT0	0x00000001

#define BIT1	0x00000002
@@ -300,7 +299,6 @@ 
#define CONFIG3 0x0059

#define CONFIG4 0x005A

#ifdef CONFIG_RTL8185B

#ifdef CONFIG_RTL818X_S

	// SD3 szuyitasi: Mac0x57= CC -> B0 Mac0x60= D1 -> C6

	// Mac0x60 = 0x000004C6 power save parameters

	#define ANAPARM_ASIC_ON    0xB0054D00
@@ -308,14 +306,6 @@ 


	#define ANAPARM_ON ANAPARM_ASIC_ON

	#define ANAPARM2_ON ANAPARM2_ASIC_ON

#else

	// SD3 CMLin:

	#define ANAPARM_ASIC_ON    0x45090658

	#define ANAPARM2_ASIC_ON  0x727f3f52



	#define ANAPARM_ON ANAPARM_ASIC_ON

	#define ANAPARM2_ON ANAPARM2_ASIC_ON

#endif

#endif



#define TESTR 0x005B
@@ -453,9 +443,7 @@ 


/* 0x00DA - 0x00DB - reserved */



#ifdef CONFIG_RTL818X_S

#define PHYPR			0xDA			//0xDA - 0x0B PHY Parameter Register.

#endif



#define CWR 0x00DC

#define CWR_END 0x00DD
@@ -468,9 +456,7 @@ 
#define RDSAR_END 0x00E7



/* 0x00E8 - 0x00EF - reserved */

#ifdef CONFIG_RTL818X_S

#define LED_CONTROL		0xED

#endif



#define FER 0x00F0

#define FER_END 0x00F3
@@ -827,11 +813,9 @@ 
#define AC_BE_PARAM		0xF8			// AC_BE Parameters Record

#define AC_BK_PARAM		0xFC			// AC_BK Parameters Record



#ifdef CONFIG_RTL818X_S

#define BcnTimingAdjust	0x16A			// Beacon Timing Adjust Register.

#define GPIOCtrl			0x16B			// GPIO Control Register.

#define PSByGC			0x180			// 0x180 - 0x183 Power Saving by Gated Clock.

#endif

#define ARFR			0x1E0	// Auto Rate Fallback Register (0x1e0 ~ 0x1e2)



#define RFSW_CTRL			0x272	// 0x272-0x273.
@@ -840,10 +824,8 @@ 
#define SW_3W_CMD0			0x27C	// Software 3-wire Control/Status Register.

#define SW_3W_CMD1			0x27D	// Software 3-wire Control/Status Register.



#ifdef CONFIG_RTL818X_S

#define PI_DATA_READ		0X360	// 0x360 - 0x361  Parallel Interface Data Register.

#define SI_DATA_READ		0x362	// 0x362 - 0x363  Serial Interface Data Register.

#endif



//----------------------------------------------------------------------------

//       8185B TPPoll bits 				(offset 0xd9, 1 byte)

drivers/staging/rtl8187se/r8180_rtl8225.c

+0 −21
Original line number Diff line number Diff line
@@ -38,7 +38,6 @@ u8 rtl8225_init_gain[]={ 
	0x93,0x38,0x5a,0xc5,//0x00,0x31,0x06,0x99,//Gain = 6 ~ -54dbm

};

#endif

#ifdef CONFIG_RTL818X_S

u32 rtl8225_chan[] ={

              0,

		0x0080, //ch1
@@ -56,26 +55,6 @@ u32 rtl8225_chan[] ={ 
		0x0680,

		0x074A, //ch14

};

#else

u32 rtl8225_chan[] = {

	0,	//dummy channel 0

	0x085c, //1

	0x08dc, //2

	0x095c, //3

	0x09dc, //4

	0x0a5c, //5

	0x0adc, //6

	0x0b5c, //7

	0x0bdc, //8

	0x0c5c, //9

	0x0cdc, //10

	0x0d5c, //11

	0x0ddc, //12

	0x0e5c, //13

	//0x0f5c, //14

	0x0f72, // 14

};

#endif



u16 rtl8225bcd_rxgain[]={

	0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,