Commit 553d12b2 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
Browse files

clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe clocks 



Use newly defined clk_regmap_phy_mux_ops for PCIe pipe clocks to let
the clock framework automatically park the clock when the clock is
switched off and restore the parent when the clock is switched on.

Reviewed-by: default avatarJohan Hovold <johan+linaro@kernel.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220608105238.2973600-4-dmitry.baryshkov@linaro.org
parent 7ee9d2e8

drivers/clk/qcom/gcc-sc7280.c

+15 −34
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include "clk-rcg.h"

#include "clk-regmap-divider.h"

#include "clk-regmap-mux.h"

#include "clk-regmap-phy-mux.h"

#include "common.h"

#include "gdsc.h"

#include "reset.h"
@@ -255,26 +256,6 @@ static const struct clk_parent_data gcc_parent_data_5[] = { 
	{ .hw = &gcc_gpll0_out_even.clkr.hw },

};



static const struct parent_map gcc_parent_map_6[] = {

	{ P_PCIE_0_PIPE_CLK, 0 },

	{ P_BI_TCXO, 2 },

};



static const struct clk_parent_data gcc_parent_data_6[] = {

	{ .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" },

	{ .fw_name = "bi_tcxo" },

};



static const struct parent_map gcc_parent_map_7[] = {

	{ P_PCIE_1_PIPE_CLK, 0 },

	{ P_BI_TCXO, 2 },

};



static const struct clk_parent_data gcc_parent_data_7[] = {

	{ .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk" },

	{ .fw_name = "bi_tcxo" },

};



static const struct parent_map gcc_parent_map_8[] = {

	{ P_BI_TCXO, 0 },

	{ P_GCC_GPLL0_OUT_MAIN, 1 },
@@ -369,32 +350,32 @@ static const struct clk_parent_data gcc_parent_data_15[] = { 
	{ .hw = &gcc_mss_gpll0_main_div_clk_src.clkr.hw },

};



static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {

static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {

	.reg = 0x6b054,

	.shift = 0,

	.width = 2,

	.parent_map = gcc_parent_map_6,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_0_pipe_clk_src",

			.parent_data = gcc_parent_data_6,

			.num_parents = ARRAY_SIZE(gcc_parent_data_6),

			.ops = &clk_regmap_mux_closest_ops,

			.parent_data = &(const struct clk_parent_data){

				.fw_name = "pcie_0_pipe_clk",

				.name = "pcie_0_pipe_clk",

			},

			.num_parents = 1,

			.ops = &clk_regmap_phy_mux_ops,

		},

	},

};



static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {

static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {

	.reg = 0x8d054,

	.shift = 0,

	.width = 2,

	.parent_map = gcc_parent_map_7,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_1_pipe_clk_src",

			.parent_data = gcc_parent_data_7,

			.num_parents = ARRAY_SIZE(gcc_parent_data_7),

			.ops = &clk_regmap_mux_closest_ops,

			.parent_data = &(const struct clk_parent_data){

				.fw_name = "pcie_1_pipe_clk",

				.name = "pcie_1_pipe_clk",

			},

			.num_parents = 1,

			.ops = &clk_regmap_phy_mux_ops,

		},

	},

};