Commit 5559c7ba authored by Qingqing Zhuo's avatar Qingqing Zhuo Committed by Alex Deucher
Browse files

drm/amd/display: Add DCN315 DMUB 



Add support for the DMUB firmware for DCN 3.1.5.

Signed-off-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 92d0c2eb

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

+1 −0
Original line number Diff line number Diff line
@@ -98,6 +98,7 @@ enum dmub_asic { 
	DMUB_ASIC_DCN303,

	DMUB_ASIC_DCN31,

	DMUB_ASIC_DCN31B,

	DMUB_ASIC_DCN315,

	DMUB_ASIC_DCN316,

	DMUB_ASIC_MAX,

};

drivers/gpu/drm/amd/display/dmub/src/Makefile

+1 −3
Original line number Diff line number Diff line
@@ -22,9 +22,7 @@ 


DMUB = dmub_srv.o dmub_srv_stat.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o

DMUB += dmub_dcn30.o dmub_dcn301.o dmub_dcn302.o dmub_dcn303.o



DMUB += dmub_dcn31.o

DMUB += dmub_dcn316.o

DMUB += dmub_dcn31.o dmub_dcn315.o dmub_dcn316.o



AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn315.c

0 → 100644
+62 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2021 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */



#include "../dmub_srv.h"

#include "dmub_reg.h"

#include "dmub_dcn315.h"



#include "dcn/dcn_3_1_5_offset.h"

#include "dcn/dcn_3_1_5_sh_mask.h"



#define DCN_BASE__INST0_SEG0                       0x00000012

#define DCN_BASE__INST0_SEG1                       0x000000C0

#define DCN_BASE__INST0_SEG2                       0x000034C0

#define DCN_BASE__INST0_SEG3                       0x00009000

#define DCN_BASE__INST0_SEG4                       0x02403C00

#define DCN_BASE__INST0_SEG5                       0



#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg

#define CTX dmub

#define REGS dmub->regs_dcn31

#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)



/* Registers. */



const struct dmub_srv_dcn31_regs dmub_srv_dcn315_regs = {

#define DMUB_SR(reg) REG_OFFSET_EXP(reg),

	{

		DMUB_DCN31_REGS()

		DMCUB_INTERNAL_REGS()

	},

#undef DMUB_SR



#define DMUB_SF(reg, field) FD_MASK(reg, field),

	{ DMUB_DCN315_FIELDS() },

#undef DMUB_SF



#define DMUB_SF(reg, field) FD_SHIFT(reg, field),

	{ DMUB_DCN315_FIELDS() },

#undef DMUB_SF

};

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn315.h

0 → 100644
+68 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2021 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */



#ifndef _DMUB_DCN315_H_

#define _DMUB_DCN315_H_



#include "dmub_dcn31.h"



#define DMUB_DCN315_FIELDS() \

	DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \

	DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \

	DMUB_SF(DMCUB_CNTL2, DMCUB_SOFT_RESET) \

	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \

	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \

	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS) \

	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \

	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \

	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \

	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \

	DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \

	DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \

	DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \

	DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \

	DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \

	DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \

	DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \

	DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \

	DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \

	DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \

	DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \

	DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \

	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \

	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \

	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \

	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \

	DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \

	DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \

	DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \

	DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) \

	DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR) \

	DMUB_SF(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT2_INT_EN) \

	DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT2_INT_ACK)



extern const struct dmub_srv_dcn31_regs dmub_srv_dcn315_regs;



#endif /* _DMUB_DCN315_H_ */

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

+7 −2
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 
#include "dmub_dcn302.h"

#include "dmub_dcn303.h"

#include "dmub_dcn31.h"

#include "dmub_dcn315.h"

#include "dmub_dcn316.h"

#include "os_types.h"

/*
@@ -221,10 +222,14 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 


	case DMUB_ASIC_DCN31:

	case DMUB_ASIC_DCN31B:

	case DMUB_ASIC_DCN315:

	case DMUB_ASIC_DCN316:

		dmub->regs_dcn31 = &dmub_srv_dcn31_regs;

		if (asic == DMUB_ASIC_DCN316)

		if (asic == DMUB_ASIC_DCN315)

			dmub->regs_dcn31 = &dmub_srv_dcn315_regs;

		else if (asic == DMUB_ASIC_DCN316)

			dmub->regs_dcn31 = &dmub_srv_dcn316_regs;

		else

			dmub->regs_dcn31 = &dmub_srv_dcn31_regs;

		funcs->reset = dmub_dcn31_reset;

		funcs->reset_release = dmub_dcn31_reset_release;

		funcs->backdoor_load = dmub_dcn31_backdoor_load;