Commit 555fd70c authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/pp: Not call cgs interface to get display info 



DC/Non DC all will update display configuration
when the display state changed
No need to get display info through cgs interface

Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d91ea496

drivers/gpu/drm/amd/powerplay/amd_powerplay.c

+1 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ static int amd_powerplay_create(struct amdgpu_device *adev) 
	hwmgr->chip_family = adev->family;

	hwmgr->chip_id = adev->asic_type;

	hwmgr->feature_mask = amdgpu_pp_feature_mask;

	hwmgr->display_config = &adev->pm.pm_display_cfg;

	adev->powerplay.pp_handle = hwmgr;

	adev->powerplay.pp_funcs = &pp_dpm_funcs;

	return 0;

drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c

+3 −5
Original line number Diff line number Diff line
@@ -265,13 +265,11 @@ int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr, 
	if (display_config == NULL)

		return -EINVAL;



	hwmgr->display_config = *display_config;



	if (NULL != hwmgr->hwmgr_func->set_deep_sleep_dcefclk)

		hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, hwmgr->display_config.min_dcef_deep_sleep_set_clk);

		hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk);



	for (index = 0; index < hwmgr->display_config.num_path_including_non_display; index++) {

		if (hwmgr->display_config.displays[index].controller_id != 0)

	for (index = 0; index < display_config->num_path_including_non_display; index++) {

		if (display_config->displays[index].controller_id != 0)

			number_of_active_display++;

	}

drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

+1 −1
Original line number Diff line number Diff line
@@ -161,7 +161,7 @@ static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input) 
	struct PP_Clocks clocks = {0};

	struct pp_display_clock_request clock_req;



	clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk;

	clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;

	clock_req.clock_type = amd_pp_dcf_clock;

	clock_req.clock_freq_in_khz = clocks.dcefClock * 10;

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

+15 −41
Original line number Diff line number Diff line
@@ -2777,8 +2777,6 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 
	struct PP_Clocks minimum_clocks = {0};

	bool disable_mclk_switching;

	bool disable_mclk_switching_for_frame_lock;

	struct cgs_display_info info = {0};

	struct cgs_mode_info mode_info = {0};

	const struct phm_clock_and_voltage_limits *max_limits;

	uint32_t i;

	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -2787,7 +2785,6 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 
	int32_t count;

	int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;



	info.mode_info = &mode_info;

	data->battery_state = (PP_StateUILabel_Battery ==

			request_ps->classification.ui_label);
@@ -2809,10 +2806,8 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 
		}

	}



	cgs_get_active_displays_info(hwmgr->device, &info);



	minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;

	minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;

	minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;

	minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;



	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,

			PHM_PlatformCaps_StablePState)) {
@@ -2843,12 +2838,12 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 
				    PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);





	if (info.display_count == 0)

	if (hwmgr->display_config->num_display == 0)

		disable_mclk_switching = false;

	else

		disable_mclk_switching = ((1 < info.display_count) ||

		disable_mclk_switching = ((1 < hwmgr->display_config->num_display) ||

					  disable_mclk_switching_for_frame_lock ||

					  smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us));

					  smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time));



	sclk = smu7_ps->performance_levels[0].engine_clock;

	mclk = smu7_ps->performance_levels[0].memory_clock;
@@ -3479,7 +3474,6 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons 
			[smu7_ps->performance_level_count - 1].memory_clock;

	struct PP_Clocks min_clocks = {0};

	uint32_t i;

	struct cgs_display_info info = {0};



	for (i = 0; i < sclk_table->count; i++) {

		if (sclk == sclk_table->dpm_levels[i].value)
@@ -3506,9 +3500,8 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons 
	if (i >= mclk_table->count)

		data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;



	cgs_get_active_displays_info(hwmgr->device, &info);



	if (data->display_timing.num_existing_displays != info.display_count)

	if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)

		data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;



	return 0;
@@ -3907,15 +3900,8 @@ smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) 
static int

smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)

{

	uint32_t num_active_displays = 0;

	struct cgs_display_info info = {0};



	info.mode_info = NULL;

	cgs_get_active_displays_info(hwmgr->device, &info);



	num_active_displays = info.display_count;



	if (num_active_displays > 1 && hwmgr->display_config.multi_monitor_in_sync != true)

	if (hwmgr->display_config->num_display > 1 &&

			!hwmgr->display_config->multi_monitor_in_sync)

		smu7_notify_smc_display_change(hwmgr, false);



	return 0;
@@ -3930,33 +3916,24 @@ smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) 
static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)

{

	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);

	uint32_t num_active_displays = 0;

	uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);

	uint32_t display_gap2;

	uint32_t pre_vbi_time_in_us;

	uint32_t frame_time_in_us;

	uint32_t ref_clock;

	uint32_t refresh_rate = 0;

	struct cgs_display_info info = {0};

	struct cgs_mode_info mode_info = {0};

	uint32_t ref_clock, refresh_rate;



	info.mode_info = &mode_info;

	cgs_get_active_displays_info(hwmgr->device, &info);

	num_active_displays = info.display_count;



	display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);

	display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);

	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);



	ref_clock =  amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);



	refresh_rate = mode_info.refresh_rate;

	refresh_rate = hwmgr->display_config->vrefresh;



	if (0 == refresh_rate)

		refresh_rate = 60;



	frame_time_in_us = 1000000 / refresh_rate;



	pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;

	pre_vbi_time_in_us = frame_time_in_us - 200 - hwmgr->display_config->min_vblank_time;



	data->frame_time_x2 = frame_time_in_us * 2 / 100;
@@ -4036,17 +4013,14 @@ smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) 
{

	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);

	bool is_update_required = false;

	struct cgs_display_info info = {0, 0, NULL};



	cgs_get_active_displays_info(hwmgr->device, &info);



	if (data->display_timing.num_existing_displays != info.display_count)

	if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)

		is_update_required = true;



	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {

		if (data->display_timing.min_clock_in_sr != hwmgr->display_config.min_core_set_clock_in_sr &&

		if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr &&

			(data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK ||

			hwmgr->display_config.min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))

			hwmgr->display_config->min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))

			is_update_required = true;

	}

	return is_update_required;

drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

+5 −9
Original line number Diff line number Diff line
@@ -693,7 +693,7 @@ static int smu8_update_sclk_limit(struct pp_hwmgr *hwmgr) 
	else

		data->sclk_dpm.soft_max_clk  = table->entries[table->count - 1].clk;



	clock = hwmgr->display_config.min_core_set_clock;

	clock = hwmgr->display_config->min_core_set_clock;

	if (clock == 0)

		pr_debug("min_core_set_clock not set\n");
@@ -748,7 +748,7 @@ static int smu8_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr) 
{

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,

				PHM_PlatformCaps_SclkDeepSleep)) {

		uint32_t clks = hwmgr->display_config.min_core_set_clock_in_sr;

		uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr;

		if (clks == 0)

			clks = SMU8_MIN_DEEP_SLEEP_SCLK;
@@ -1040,25 +1040,21 @@ static int smu8_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 
	struct smu8_hwmgr *data = hwmgr->backend;

	struct PP_Clocks clocks = {0, 0, 0, 0};

	bool force_high;

	uint32_t  num_of_active_displays = 0;

	struct cgs_display_info info = {0};



	smu8_ps->need_dfs_bypass = true;



	data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);



	clocks.memoryClock = hwmgr->display_config.min_mem_set_clock != 0 ?

				hwmgr->display_config.min_mem_set_clock :

	clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ?

				hwmgr->display_config->min_mem_set_clock :

				data->sys_info.nbp_memory_clock[1];



	cgs_get_active_displays_info(hwmgr->device, &info);

	num_of_active_displays = info.display_count;



	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))

		clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;



	force_high = (clocks.memoryClock > data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1])

			|| (num_of_active_displays >= 3);

			|| (hwmgr->display_config->num_display >= 3);



	smu8_ps->action = smu8_current_ps->action;