Commit 563fcfbf authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: add hdp version 6 functions 



Unify hdp related function into hdp structure for hdp version 6.
V2: Remove hdp invalidate function as hdp v6 doesn't have read cache.

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 068421b1

drivers/gpu/drm/amd/amdgpu/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -75,7 +75,7 @@ amdgpu-y += \ 
	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \

	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o mxgpu_nv.o \

	nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o \

	nbio_v4_3.o

	nbio_v4_3.o hdp_v6_0.o



# add DF block

amdgpu-y += \

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+2 −1
Original line number Diff line number Diff line
@@ -1188,7 +1188,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev); 
#define amdgpu_asic_flush_hdp(adev, r) \

	((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))

#define amdgpu_asic_invalidate_hdp(adev, r) \

	((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r)))

	((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \

	 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : 0))

#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))

#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))

#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

0 → 100644
+100 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2020 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#include "amdgpu.h"

#include "amdgpu_atombios.h"

#include "hdp_v6_0.h"



#include "hdp/hdp_6_0_0_offset.h"

#include "hdp/hdp_6_0_0_sh_mask.h"

#include <uapi/linux/kfd_ioctl.h>



static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,

				struct amdgpu_ring *ring)

{

	if (!ring || !ring->funcs->emit_wreg)

		WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);

	else

		amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);

}



static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,

						      bool enable)

{

	uint32_t hdp_clk_cntl;



	if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))

		return;



	hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);



	if (enable) {

		hdp_clk_cntl &=

			~(uint32_t)

			(HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |

			 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |

			 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |

			 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |

			 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |

			 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);

	} else {

		hdp_clk_cntl |= HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |

			HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |

			HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |

			HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |

			HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |

			HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;

	}



	WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);

}



static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev,

					    u64 *flags)

{

	uint32_t tmp;



	/* AMD_CG_SUPPORT_HDP_MGCG */

	tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);

	if (!(tmp & (HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |

		     HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |

		     HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |

		     HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |

		     HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |

		     HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))

		*flags |= AMD_CG_SUPPORT_HDP_MGCG;



	/* AMD_CG_SUPPORT_HDP_LS/DS/SD */

	tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);

	if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)

		*flags |= AMD_CG_SUPPORT_HDP_LS;

	else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK)

		*flags |= AMD_CG_SUPPORT_HDP_DS;

	else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK)

		*flags |= AMD_CG_SUPPORT_HDP_SD;

}



const struct amdgpu_hdp_funcs hdp_v6_0_funcs = {

	.flush_hdp = hdp_v6_0_flush_hdp,

	.update_clock_gating = hdp_v6_0_update_clock_gating,

	.get_clock_gating_state = hdp_v6_0_get_clockgating_state,

};

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.h

0 → 100644
+31 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2020 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef __HDP_V6_0_H__

#define __HDP_V6_0_H__



#include "soc15_common.h"



extern const struct amdgpu_hdp_funcs hdp_v6_0_funcs;



#endif