Loading arch/arm/boot/dts/imx53-m53evk.dts +1 −1 Original line number Diff line number Diff line Loading @@ -146,7 +146,7 @@ sgtl5000: codec@0a { reg = <0x0a>; VDDA-supply = <®_3p2v>; VDDIO-supply = <®_3p2v>; clocks = <&clks 150>; clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; }; }; Loading arch/arm/boot/dts/imx53-mba53.dts +1 −1 Original line number Diff line number Diff line Loading @@ -163,7 +163,7 @@ &i2c2 { codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks 150>; clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; VDDA-supply = <®_3p2v>; VDDIO-supply = <®_3p2v>; }; Loading arch/arm/boot/dts/imx53-qsb.dts +1 −1 Original line number Diff line number Diff line Loading @@ -291,7 +291,7 @@ sgtl5000: codec@0a { reg = <0x0a>; VDDA-supply = <®_3p2v>; VDDIO-supply = <®_3p2v>; clocks = <&clks 150>; clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; }; }; Loading arch/arm/boot/dts/imx53.dtsi +77 −45 Original line number Diff line number Diff line Loading @@ -12,6 +12,7 @@ #include "skeleton.dtsi" #include "imx53-pinfunc.h" #include <dt-bindings/clock/imx5-clock.h> / { aliases { Loading Loading @@ -89,7 +90,9 @@ ipu: ipu@18000000 { compatible = "fsl,imx53-ipu"; reg = <0x18000000 0x080000000>; interrupts = <11 10>; clocks = <&clks 59>, <&clks 110>, <&clks 61>; clocks = <&clks IMX5_CLK_IPU_GATE>, <&clks IMX5_CLK_IPU_DI0_GATE>, <&clks IMX5_CLK_IPU_DI1_GATE>; clock-names = "bus", "di0", "di1"; resets = <&src 2>; }; Loading @@ -112,7 +115,9 @@ esdhc1: esdhc@50004000 { compatible = "fsl,imx53-esdhc"; reg = <0x50004000 0x4000>; interrupts = <1>; clocks = <&clks 44>, <&clks 0>, <&clks 71>; clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, <&clks IMX5_CLK_DUMMY>, <&clks IMX5_CLK_ESDHC1_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; Loading @@ -122,7 +127,9 @@ esdhc2: esdhc@50008000 { compatible = "fsl,imx53-esdhc"; reg = <0x50008000 0x4000>; interrupts = <2>; clocks = <&clks 45>, <&clks 0>, <&clks 72>; clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, <&clks IMX5_CLK_DUMMY>, <&clks IMX5_CLK_ESDHC2_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; Loading @@ -132,7 +139,8 @@ uart3: serial@5000c000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x5000c000 0x4000>; interrupts = <33>; clocks = <&clks 32>, <&clks 33>; clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, <&clks IMX5_CLK_UART3_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading @@ -143,7 +151,8 @@ ecspi1: ecspi@50010000 { compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; reg = <0x50010000 0x4000>; interrupts = <36>; clocks = <&clks 51>, <&clks 52>; clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, <&clks IMX5_CLK_ECSPI1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading @@ -152,7 +161,7 @@ ssi2: ssi@50014000 { compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; reg = <0x50014000 0x4000>; interrupts = <30>; clocks = <&clks 49>; clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; dmas = <&sdma 24 1 0>, <&sdma 25 1 0>; dma-names = "rx", "tx"; Loading @@ -165,7 +174,9 @@ esdhc3: esdhc@50020000 { compatible = "fsl,imx53-esdhc"; reg = <0x50020000 0x4000>; interrupts = <3>; clocks = <&clks 46>, <&clks 0>, <&clks 73>; clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, <&clks IMX5_CLK_DUMMY>, <&clks IMX5_CLK_ESDHC3_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; Loading @@ -175,7 +186,9 @@ esdhc4: esdhc@50024000 { compatible = "fsl,imx53-esdhc"; reg = <0x50024000 0x4000>; interrupts = <4>; clocks = <&clks 47>, <&clks 0>, <&clks 74>; clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, <&clks IMX5_CLK_DUMMY>, <&clks IMX5_CLK_ESDHC4_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; Loading @@ -184,14 +197,14 @@ esdhc4: esdhc@50024000 { usbphy0: usbphy@0 { compatible = "usb-nop-xceiv"; clocks = <&clks 124>; clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; clock-names = "main_clk"; status = "okay"; }; usbphy1: usbphy@1 { compatible = "usb-nop-xceiv"; clocks = <&clks 125>; clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; clock-names = "main_clk"; status = "okay"; }; Loading @@ -200,7 +213,7 @@ usbotg: usb@53f80000 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80000 0x0200>; interrupts = <18>; clocks = <&clks 108>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 0>; fsl,usbphy = <&usbphy0>; status = "disabled"; Loading @@ -210,7 +223,7 @@ usbh1: usb@53f80200 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80200 0x0200>; interrupts = <14>; clocks = <&clks 108>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 1>; fsl,usbphy = <&usbphy1>; status = "disabled"; Loading @@ -220,7 +233,7 @@ usbh2: usb@53f80400 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80400 0x0200>; interrupts = <16>; clocks = <&clks 108>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 2>; status = "disabled"; }; Loading @@ -229,7 +242,7 @@ usbh3: usb@53f80600 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80600 0x0200>; interrupts = <17>; clocks = <&clks 108>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 3>; status = "disabled"; }; Loading @@ -238,7 +251,7 @@ usbmisc: usbmisc@53f80800 { #index-cells = <1>; compatible = "fsl,imx53-usbmisc"; reg = <0x53f80800 0x200>; clocks = <&clks 108>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; }; gpio1: gpio@53f84000 { Loading Loading @@ -285,7 +298,7 @@ kpp: kpp@53f94000 { compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; reg = <0x53f94000 0x4000>; interrupts = <60>; clocks = <&clks 0>; clocks = <&clks IMX5_CLK_DUMMY>; status = "disabled"; }; Loading @@ -293,14 +306,14 @@ wdog1: wdog@53f98000 { compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; reg = <0x53f98000 0x4000>; interrupts = <58>; clocks = <&clks 0>; clocks = <&clks IMX5_CLK_DUMMY>; }; wdog2: wdog@53f9c000 { compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; reg = <0x53f9c000 0x4000>; interrupts = <59>; clocks = <&clks 0>; clocks = <&clks IMX5_CLK_DUMMY>; status = "disabled"; }; Loading @@ -308,7 +321,8 @@ gpt: timer@53fa0000 { compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; reg = <0x53fa0000 0x4000>; interrupts = <39>; clocks = <&clks 36>, <&clks 41>; clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, <&clks IMX5_CLK_GPT_HF_GATE>; clock-names = "ipg", "per"; }; Loading @@ -328,9 +342,12 @@ ldb: ldb@53fa8008 { compatible = "fsl,imx53-ldb"; reg = <0x53fa8008 0x4>; gpr = <&gpr>; clocks = <&clks 122>, <&clks 120>, <&clks 115>, <&clks 116>, <&clks 123>, <&clks 85>; clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, <&clks IMX5_CLK_LDB_DI1_SEL>, <&clks IMX5_CLK_IPU_DI0_SEL>, <&clks IMX5_CLK_IPU_DI1_SEL>, <&clks IMX5_CLK_LDB_DI0_GATE>, <&clks IMX5_CLK_LDB_DI1_GATE>; clock-names = "di0_pll", "di1_pll", "di0_sel", "di1_sel", "di0", "di1"; Loading @@ -353,7 +370,8 @@ pwm1: pwm@53fb4000 { #pwm-cells = <2>; compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; reg = <0x53fb4000 0x4000>; clocks = <&clks 37>, <&clks 38>; clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, <&clks IMX5_CLK_PWM1_HF_GATE>; clock-names = "ipg", "per"; interrupts = <61>; }; Loading @@ -362,7 +380,8 @@ pwm2: pwm@53fb8000 { #pwm-cells = <2>; compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; reg = <0x53fb8000 0x4000>; clocks = <&clks 39>, <&clks 40>; clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, <&clks IMX5_CLK_PWM2_HF_GATE>; clock-names = "ipg", "per"; interrupts = <94>; }; Loading @@ -371,7 +390,8 @@ uart1: serial@53fbc000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53fbc000 0x4000>; interrupts = <31>; clocks = <&clks 28>, <&clks 29>; clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, <&clks IMX5_CLK_UART1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading @@ -380,7 +400,8 @@ uart2: serial@53fc0000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53fc0000 0x4000>; interrupts = <32>; clocks = <&clks 30>, <&clks 31>; clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, <&clks IMX5_CLK_UART2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading @@ -389,7 +410,8 @@ can1: can@53fc8000 { compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; reg = <0x53fc8000 0x4000>; interrupts = <82>; clocks = <&clks 158>, <&clks 157>; clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading @@ -398,7 +420,8 @@ can2: can@53fcc000 { compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; reg = <0x53fcc000 0x4000>; interrupts = <83>; clocks = <&clks 87>, <&clks 86>; clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, <&clks IMX5_CLK_CAN2_SERIAL_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading Loading @@ -452,7 +475,7 @@ i2c3: i2c@53fec000 { compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; reg = <0x53fec000 0x4000>; interrupts = <64>; clocks = <&clks 88>; clocks = <&clks IMX5_CLK_I2C3_GATE>; status = "disabled"; }; Loading @@ -460,7 +483,8 @@ uart4: serial@53ff0000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53ff0000 0x4000>; interrupts = <13>; clocks = <&clks 65>, <&clks 66>; clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, <&clks IMX5_CLK_UART4_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading @@ -477,14 +501,15 @@ iim: iim@63f98000 { compatible = "fsl,imx53-iim", "fsl,imx27-iim"; reg = <0x63f98000 0x4000>; interrupts = <69>; clocks = <&clks 107>; clocks = <&clks IMX5_CLK_IIM_GATE>; }; uart5: serial@63f90000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x63f90000 0x4000>; interrupts = <86>; clocks = <&clks 67>, <&clks 68>; clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, <&clks IMX5_CLK_UART5_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading @@ -492,7 +517,7 @@ uart5: serial@63f90000 { owire: owire@63fa4000 { compatible = "fsl,imx53-owire", "fsl,imx21-owire"; reg = <0x63fa4000 0x4000>; clocks = <&clks 159>; clocks = <&clks IMX5_CLK_OWIRE_GATE>; status = "disabled"; }; Loading @@ -502,7 +527,8 @@ ecspi2: ecspi@63fac000 { compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; reg = <0x63fac000 0x4000>; interrupts = <37>; clocks = <&clks 53>, <&clks 54>; clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, <&clks IMX5_CLK_ECSPI2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading @@ -511,7 +537,8 @@ sdma: sdma@63fb0000 { compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; reg = <0x63fb0000 0x4000>; interrupts = <6>; clocks = <&clks 56>, <&clks 56>; clocks = <&clks IMX5_CLK_SDMA_GATE>, <&clks IMX5_CLK_SDMA_GATE>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; Loading @@ -523,7 +550,8 @@ cspi: cspi@63fc0000 { compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; reg = <0x63fc0000 0x4000>; interrupts = <38>; clocks = <&clks 55>, <&clks 55>; clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, <&clks IMX5_CLK_CSPI_IPG_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading @@ -534,7 +562,7 @@ i2c2: i2c@63fc4000 { compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; reg = <0x63fc4000 0x4000>; interrupts = <63>; clocks = <&clks 35>; clocks = <&clks IMX5_CLK_I2C2_GATE>; status = "disabled"; }; Loading @@ -544,7 +572,7 @@ i2c1: i2c@63fc8000 { compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; reg = <0x63fc8000 0x4000>; interrupts = <62>; clocks = <&clks 34>; clocks = <&clks IMX5_CLK_I2C1_GATE>; status = "disabled"; }; Loading @@ -552,7 +580,7 @@ ssi1: ssi@63fcc000 { compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; reg = <0x63fcc000 0x4000>; interrupts = <29>; clocks = <&clks 48>; clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; dmas = <&sdma 28 0 0>, <&sdma 29 0 0>; dma-names = "rx", "tx"; Loading @@ -571,7 +599,7 @@ nfc: nand@63fdb000 { compatible = "fsl,imx53-nand"; reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; interrupts = <8>; clocks = <&clks 60>; clocks = <&clks IMX5_CLK_NFC_GATE>; status = "disabled"; }; Loading @@ -579,7 +607,7 @@ ssi3: ssi@63fe8000 { compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; reg = <0x63fe8000 0x4000>; interrupts = <96>; clocks = <&clks 50>; clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; dmas = <&sdma 46 0 0>, <&sdma 47 0 0>; dma-names = "rx", "tx"; Loading @@ -592,7 +620,9 @@ fec: ethernet@63fec000 { compatible = "fsl,imx53-fec", "fsl,imx25-fec"; reg = <0x63fec000 0x4000>; interrupts = <87>; clocks = <&clks 42>, <&clks 42>, <&clks 42>; clocks = <&clks IMX5_CLK_FEC_GATE>, <&clks IMX5_CLK_FEC_GATE>, <&clks IMX5_CLK_FEC_GATE>; clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; Loading @@ -601,7 +631,8 @@ tve: tve@63ff0000 { compatible = "fsl,imx53-tve"; reg = <0x63ff0000 0x1000>; interrupts = <92>; clocks = <&clks 69>, <&clks 116>; clocks = <&clks IMX5_CLK_TVE_GATE>, <&clks IMX5_CLK_IPU_DI1_SEL>; clock-names = "tve", "di_sel"; crtcs = <&ipu 1>; status = "disabled"; Loading @@ -611,7 +642,8 @@ vpu: vpu@63ff4000 { compatible = "fsl,imx53-vpu"; reg = <0x63ff4000 0x1000>; interrupts = <9>; clocks = <&clks 63>, <&clks 63>; clocks = <&clks IMX5_CLK_VPU_GATE>, <&clks IMX5_CLK_VPU_GATE>; clock-names = "per", "ahb"; iram = <&ocram>; status = "disabled"; Loading @@ -621,7 +653,7 @@ vpu: vpu@63ff4000 { ocram: sram@f8000000 { compatible = "mmio-sram"; reg = <0xf8000000 0x20000>; clocks = <&clks 186>; clocks = <&clks IMX5_CLK_OCRAM>; }; }; }; Loading
arch/arm/boot/dts/imx53-m53evk.dts +1 −1 Original line number Diff line number Diff line Loading @@ -146,7 +146,7 @@ sgtl5000: codec@0a { reg = <0x0a>; VDDA-supply = <®_3p2v>; VDDIO-supply = <®_3p2v>; clocks = <&clks 150>; clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; }; }; Loading
arch/arm/boot/dts/imx53-mba53.dts +1 −1 Original line number Diff line number Diff line Loading @@ -163,7 +163,7 @@ &i2c2 { codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks 150>; clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; VDDA-supply = <®_3p2v>; VDDIO-supply = <®_3p2v>; }; Loading
arch/arm/boot/dts/imx53-qsb.dts +1 −1 Original line number Diff line number Diff line Loading @@ -291,7 +291,7 @@ sgtl5000: codec@0a { reg = <0x0a>; VDDA-supply = <®_3p2v>; VDDIO-supply = <®_3p2v>; clocks = <&clks 150>; clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; }; }; Loading
arch/arm/boot/dts/imx53.dtsi +77 −45 Original line number Diff line number Diff line Loading @@ -12,6 +12,7 @@ #include "skeleton.dtsi" #include "imx53-pinfunc.h" #include <dt-bindings/clock/imx5-clock.h> / { aliases { Loading Loading @@ -89,7 +90,9 @@ ipu: ipu@18000000 { compatible = "fsl,imx53-ipu"; reg = <0x18000000 0x080000000>; interrupts = <11 10>; clocks = <&clks 59>, <&clks 110>, <&clks 61>; clocks = <&clks IMX5_CLK_IPU_GATE>, <&clks IMX5_CLK_IPU_DI0_GATE>, <&clks IMX5_CLK_IPU_DI1_GATE>; clock-names = "bus", "di0", "di1"; resets = <&src 2>; }; Loading @@ -112,7 +115,9 @@ esdhc1: esdhc@50004000 { compatible = "fsl,imx53-esdhc"; reg = <0x50004000 0x4000>; interrupts = <1>; clocks = <&clks 44>, <&clks 0>, <&clks 71>; clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, <&clks IMX5_CLK_DUMMY>, <&clks IMX5_CLK_ESDHC1_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; Loading @@ -122,7 +127,9 @@ esdhc2: esdhc@50008000 { compatible = "fsl,imx53-esdhc"; reg = <0x50008000 0x4000>; interrupts = <2>; clocks = <&clks 45>, <&clks 0>, <&clks 72>; clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, <&clks IMX5_CLK_DUMMY>, <&clks IMX5_CLK_ESDHC2_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; Loading @@ -132,7 +139,8 @@ uart3: serial@5000c000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x5000c000 0x4000>; interrupts = <33>; clocks = <&clks 32>, <&clks 33>; clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, <&clks IMX5_CLK_UART3_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading @@ -143,7 +151,8 @@ ecspi1: ecspi@50010000 { compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; reg = <0x50010000 0x4000>; interrupts = <36>; clocks = <&clks 51>, <&clks 52>; clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, <&clks IMX5_CLK_ECSPI1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading @@ -152,7 +161,7 @@ ssi2: ssi@50014000 { compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; reg = <0x50014000 0x4000>; interrupts = <30>; clocks = <&clks 49>; clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; dmas = <&sdma 24 1 0>, <&sdma 25 1 0>; dma-names = "rx", "tx"; Loading @@ -165,7 +174,9 @@ esdhc3: esdhc@50020000 { compatible = "fsl,imx53-esdhc"; reg = <0x50020000 0x4000>; interrupts = <3>; clocks = <&clks 46>, <&clks 0>, <&clks 73>; clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, <&clks IMX5_CLK_DUMMY>, <&clks IMX5_CLK_ESDHC3_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; Loading @@ -175,7 +186,9 @@ esdhc4: esdhc@50024000 { compatible = "fsl,imx53-esdhc"; reg = <0x50024000 0x4000>; interrupts = <4>; clocks = <&clks 47>, <&clks 0>, <&clks 74>; clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, <&clks IMX5_CLK_DUMMY>, <&clks IMX5_CLK_ESDHC4_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; Loading @@ -184,14 +197,14 @@ esdhc4: esdhc@50024000 { usbphy0: usbphy@0 { compatible = "usb-nop-xceiv"; clocks = <&clks 124>; clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; clock-names = "main_clk"; status = "okay"; }; usbphy1: usbphy@1 { compatible = "usb-nop-xceiv"; clocks = <&clks 125>; clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; clock-names = "main_clk"; status = "okay"; }; Loading @@ -200,7 +213,7 @@ usbotg: usb@53f80000 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80000 0x0200>; interrupts = <18>; clocks = <&clks 108>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 0>; fsl,usbphy = <&usbphy0>; status = "disabled"; Loading @@ -210,7 +223,7 @@ usbh1: usb@53f80200 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80200 0x0200>; interrupts = <14>; clocks = <&clks 108>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 1>; fsl,usbphy = <&usbphy1>; status = "disabled"; Loading @@ -220,7 +233,7 @@ usbh2: usb@53f80400 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80400 0x0200>; interrupts = <16>; clocks = <&clks 108>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 2>; status = "disabled"; }; Loading @@ -229,7 +242,7 @@ usbh3: usb@53f80600 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80600 0x0200>; interrupts = <17>; clocks = <&clks 108>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 3>; status = "disabled"; }; Loading @@ -238,7 +251,7 @@ usbmisc: usbmisc@53f80800 { #index-cells = <1>; compatible = "fsl,imx53-usbmisc"; reg = <0x53f80800 0x200>; clocks = <&clks 108>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; }; gpio1: gpio@53f84000 { Loading Loading @@ -285,7 +298,7 @@ kpp: kpp@53f94000 { compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; reg = <0x53f94000 0x4000>; interrupts = <60>; clocks = <&clks 0>; clocks = <&clks IMX5_CLK_DUMMY>; status = "disabled"; }; Loading @@ -293,14 +306,14 @@ wdog1: wdog@53f98000 { compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; reg = <0x53f98000 0x4000>; interrupts = <58>; clocks = <&clks 0>; clocks = <&clks IMX5_CLK_DUMMY>; }; wdog2: wdog@53f9c000 { compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; reg = <0x53f9c000 0x4000>; interrupts = <59>; clocks = <&clks 0>; clocks = <&clks IMX5_CLK_DUMMY>; status = "disabled"; }; Loading @@ -308,7 +321,8 @@ gpt: timer@53fa0000 { compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; reg = <0x53fa0000 0x4000>; interrupts = <39>; clocks = <&clks 36>, <&clks 41>; clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, <&clks IMX5_CLK_GPT_HF_GATE>; clock-names = "ipg", "per"; }; Loading @@ -328,9 +342,12 @@ ldb: ldb@53fa8008 { compatible = "fsl,imx53-ldb"; reg = <0x53fa8008 0x4>; gpr = <&gpr>; clocks = <&clks 122>, <&clks 120>, <&clks 115>, <&clks 116>, <&clks 123>, <&clks 85>; clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, <&clks IMX5_CLK_LDB_DI1_SEL>, <&clks IMX5_CLK_IPU_DI0_SEL>, <&clks IMX5_CLK_IPU_DI1_SEL>, <&clks IMX5_CLK_LDB_DI0_GATE>, <&clks IMX5_CLK_LDB_DI1_GATE>; clock-names = "di0_pll", "di1_pll", "di0_sel", "di1_sel", "di0", "di1"; Loading @@ -353,7 +370,8 @@ pwm1: pwm@53fb4000 { #pwm-cells = <2>; compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; reg = <0x53fb4000 0x4000>; clocks = <&clks 37>, <&clks 38>; clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, <&clks IMX5_CLK_PWM1_HF_GATE>; clock-names = "ipg", "per"; interrupts = <61>; }; Loading @@ -362,7 +380,8 @@ pwm2: pwm@53fb8000 { #pwm-cells = <2>; compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; reg = <0x53fb8000 0x4000>; clocks = <&clks 39>, <&clks 40>; clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, <&clks IMX5_CLK_PWM2_HF_GATE>; clock-names = "ipg", "per"; interrupts = <94>; }; Loading @@ -371,7 +390,8 @@ uart1: serial@53fbc000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53fbc000 0x4000>; interrupts = <31>; clocks = <&clks 28>, <&clks 29>; clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, <&clks IMX5_CLK_UART1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading @@ -380,7 +400,8 @@ uart2: serial@53fc0000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53fc0000 0x4000>; interrupts = <32>; clocks = <&clks 30>, <&clks 31>; clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, <&clks IMX5_CLK_UART2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading @@ -389,7 +410,8 @@ can1: can@53fc8000 { compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; reg = <0x53fc8000 0x4000>; interrupts = <82>; clocks = <&clks 158>, <&clks 157>; clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading @@ -398,7 +420,8 @@ can2: can@53fcc000 { compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; reg = <0x53fcc000 0x4000>; interrupts = <83>; clocks = <&clks 87>, <&clks 86>; clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, <&clks IMX5_CLK_CAN2_SERIAL_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading Loading @@ -452,7 +475,7 @@ i2c3: i2c@53fec000 { compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; reg = <0x53fec000 0x4000>; interrupts = <64>; clocks = <&clks 88>; clocks = <&clks IMX5_CLK_I2C3_GATE>; status = "disabled"; }; Loading @@ -460,7 +483,8 @@ uart4: serial@53ff0000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53ff0000 0x4000>; interrupts = <13>; clocks = <&clks 65>, <&clks 66>; clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, <&clks IMX5_CLK_UART4_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading @@ -477,14 +501,15 @@ iim: iim@63f98000 { compatible = "fsl,imx53-iim", "fsl,imx27-iim"; reg = <0x63f98000 0x4000>; interrupts = <69>; clocks = <&clks 107>; clocks = <&clks IMX5_CLK_IIM_GATE>; }; uart5: serial@63f90000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x63f90000 0x4000>; interrupts = <86>; clocks = <&clks 67>, <&clks 68>; clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, <&clks IMX5_CLK_UART5_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading @@ -492,7 +517,7 @@ uart5: serial@63f90000 { owire: owire@63fa4000 { compatible = "fsl,imx53-owire", "fsl,imx21-owire"; reg = <0x63fa4000 0x4000>; clocks = <&clks 159>; clocks = <&clks IMX5_CLK_OWIRE_GATE>; status = "disabled"; }; Loading @@ -502,7 +527,8 @@ ecspi2: ecspi@63fac000 { compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; reg = <0x63fac000 0x4000>; interrupts = <37>; clocks = <&clks 53>, <&clks 54>; clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, <&clks IMX5_CLK_ECSPI2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading @@ -511,7 +537,8 @@ sdma: sdma@63fb0000 { compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; reg = <0x63fb0000 0x4000>; interrupts = <6>; clocks = <&clks 56>, <&clks 56>; clocks = <&clks IMX5_CLK_SDMA_GATE>, <&clks IMX5_CLK_SDMA_GATE>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; Loading @@ -523,7 +550,8 @@ cspi: cspi@63fc0000 { compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; reg = <0x63fc0000 0x4000>; interrupts = <38>; clocks = <&clks 55>, <&clks 55>; clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, <&clks IMX5_CLK_CSPI_IPG_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; Loading @@ -534,7 +562,7 @@ i2c2: i2c@63fc4000 { compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; reg = <0x63fc4000 0x4000>; interrupts = <63>; clocks = <&clks 35>; clocks = <&clks IMX5_CLK_I2C2_GATE>; status = "disabled"; }; Loading @@ -544,7 +572,7 @@ i2c1: i2c@63fc8000 { compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; reg = <0x63fc8000 0x4000>; interrupts = <62>; clocks = <&clks 34>; clocks = <&clks IMX5_CLK_I2C1_GATE>; status = "disabled"; }; Loading @@ -552,7 +580,7 @@ ssi1: ssi@63fcc000 { compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; reg = <0x63fcc000 0x4000>; interrupts = <29>; clocks = <&clks 48>; clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; dmas = <&sdma 28 0 0>, <&sdma 29 0 0>; dma-names = "rx", "tx"; Loading @@ -571,7 +599,7 @@ nfc: nand@63fdb000 { compatible = "fsl,imx53-nand"; reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; interrupts = <8>; clocks = <&clks 60>; clocks = <&clks IMX5_CLK_NFC_GATE>; status = "disabled"; }; Loading @@ -579,7 +607,7 @@ ssi3: ssi@63fe8000 { compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; reg = <0x63fe8000 0x4000>; interrupts = <96>; clocks = <&clks 50>; clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; dmas = <&sdma 46 0 0>, <&sdma 47 0 0>; dma-names = "rx", "tx"; Loading @@ -592,7 +620,9 @@ fec: ethernet@63fec000 { compatible = "fsl,imx53-fec", "fsl,imx25-fec"; reg = <0x63fec000 0x4000>; interrupts = <87>; clocks = <&clks 42>, <&clks 42>, <&clks 42>; clocks = <&clks IMX5_CLK_FEC_GATE>, <&clks IMX5_CLK_FEC_GATE>, <&clks IMX5_CLK_FEC_GATE>; clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; Loading @@ -601,7 +631,8 @@ tve: tve@63ff0000 { compatible = "fsl,imx53-tve"; reg = <0x63ff0000 0x1000>; interrupts = <92>; clocks = <&clks 69>, <&clks 116>; clocks = <&clks IMX5_CLK_TVE_GATE>, <&clks IMX5_CLK_IPU_DI1_SEL>; clock-names = "tve", "di_sel"; crtcs = <&ipu 1>; status = "disabled"; Loading @@ -611,7 +642,8 @@ vpu: vpu@63ff4000 { compatible = "fsl,imx53-vpu"; reg = <0x63ff4000 0x1000>; interrupts = <9>; clocks = <&clks 63>, <&clks 63>; clocks = <&clks IMX5_CLK_VPU_GATE>, <&clks IMX5_CLK_VPU_GATE>; clock-names = "per", "ahb"; iram = <&ocram>; status = "disabled"; Loading @@ -621,7 +653,7 @@ vpu: vpu@63ff4000 { ocram: sram@f8000000 { compatible = "mmio-sram"; reg = <0xf8000000 0x20000>; clocks = <&clks 186>; clocks = <&clks IMX5_CLK_OCRAM>; }; }; };