Commit 570de94b authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amdgpu: Add auto mode for compute partition



When auto mode is specified, driver will choose the right compute
partition mode.

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarLe Ma <le.ma@amd.com>
Reviewed-by: default avatarPhilip Yang <philip.yang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1589c82a
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+1 −1
Original line number Diff line number Diff line
@@ -242,7 +242,7 @@ extern int amdgpu_num_kcq;
extern int amdgpu_vcnfw_log;
extern int amdgpu_sg_display;

extern uint amdgpu_user_partt_mode;
extern int amdgpu_user_partt_mode;

#define AMDGPU_VM_MAX_NUM_CTX			4096
#define AMDGPU_SG_THRESHOLD			(256*1024*1024)
+5 −3
Original line number Diff line number Diff line
@@ -193,7 +193,7 @@ int amdgpu_smartshift_bias;
int amdgpu_use_xgmi_p2p = 1;
int amdgpu_vcnfw_log;
int amdgpu_sg_display = -1; /* auto */
uint amdgpu_user_partt_mode;
int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE;

static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);

@@ -955,8 +955,10 @@ module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
 * DOC: partition_mode (int)
 * Used to override the default SPX mode.
 */
MODULE_PARM_DESC(user_partt_mode,
	"specify partition mode to be used (0 = AMDGPU_SPX_PARTITION_MODE(default value), \
MODULE_PARM_DESC(
	user_partt_mode,
	"specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \
						0 = AMDGPU_SPX_PARTITION_MODE, \
						1 = AMDGPU_DPX_PARTITION_MODE, \
						2 = AMDGPU_TPX_PARTITION_MODE, \
						3 = AMDGPU_QPX_PARTITION_MODE, \
+2 −0
Original line number Diff line number Diff line
@@ -62,6 +62,8 @@ enum amdgpu_gfx_partition {
	AMDGPU_QPX_PARTITION_MODE = 3,
	AMDGPU_CPX_PARTITION_MODE = 4,
	AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE = -1,
	/* Automatically choose the right mode */
	AMDGPU_AUTO_COMPUTE_PARTITION_MODE = -2,
};

#define NUM_XCC(x) hweight16(x)
+27 −1
Original line number Diff line number Diff line
@@ -235,6 +235,30 @@ int __aqua_vanjaram_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id,
	return 0;
}

static enum amdgpu_gfx_partition
__aqua_vanjaram_get_auto_mode(struct amdgpu_xcp_mgr *xcp_mgr)
{
	struct amdgpu_device *adev = xcp_mgr->adev;
	int num_xcc;

	num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask);

	if (adev->gmc.num_mem_partitions == 1)
		return AMDGPU_SPX_PARTITION_MODE;

	if (adev->gmc.num_mem_partitions == num_xcc)
		return AMDGPU_CPX_PARTITION_MODE;

	if (adev->gmc.num_mem_partitions == num_xcc / 2)
		return (adev->flags & AMD_IS_APU) ? AMDGPU_TPX_PARTITION_MODE :
						    AMDGPU_QPX_PARTITION_MODE;

	if (adev->gmc.num_mem_partitions == 2 && !(adev->flags & AMD_IS_APU))
		return AMDGPU_DPX_PARTITION_MODE;

	return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE;
}

static bool __aqua_vanjaram_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr,
					  enum amdgpu_gfx_partition mode)
{
@@ -304,7 +328,9 @@ static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr,
	adev = xcp_mgr->adev;
	num_xcc = NUM_XCC(adev->gfx.xcc_mask);

	if (!__aqua_vanjaram_is_valid_mode(xcp_mgr, mode))
	if (mode == AMDGPU_AUTO_COMPUTE_PARTITION_MODE)
		mode = __aqua_vanjaram_get_auto_mode(xcp_mgr);
	else if (!__aqua_vanjaram_is_valid_mode(xcp_mgr, mode))
		return -EINVAL;

	if (adev->kfd.init_complete)