Commit 577b5c2b authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: Block 6Ghz timing if SBIOS set HDMI_6G_en to 0

parent 0f0bdca5
Loading
Loading
Loading
Loading
+1 −0
Original line number Diff line number Diff line
@@ -1853,6 +1853,7 @@ static enum bp_result bios_parser_get_encoder_cap_info(

	info->DP_HBR2_EN = record->usHBR2En;
	info->DP_HBR3_EN = record->usHBR3En;
	info->HDMI_6GB_EN = record->usHDMI6GEn;
	return BP_RESULT_OK;
}

+4 −0
Original line number Diff line number Diff line
@@ -887,6 +887,9 @@ static bool dce110_link_encoder_validate_hdmi_output(
			crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
		return false;

	if (!enc110->base.features.flags.bits.HDMI_6GB_EN &&
		adjusted_pix_clk_khz >= 300000)
		return false;
	return true;
}

@@ -1008,6 +1011,7 @@ bool dce110_link_encoder_construct(
				bp_cap_info.DP_HBR2_EN;
		enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
				bp_cap_info.DP_HBR3_EN;
		enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
	}

	return true;
+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ struct encoder_feature_support {
			uint32_t IS_TPS3_CAPABLE:1;
			uint32_t IS_TPS4_CAPABLE:1;
			uint32_t IS_YCBCR_CAPABLE:1;
			uint32_t HDMI_6GB_EN:1;
		} bits;
		uint32_t raw;
	} flags;