Loading arch/x86/include/asm/amd_iommu_types.h +1 −0 Original line number Diff line number Diff line Loading @@ -127,6 +127,7 @@ #define CMD_COMPL_WAIT 0x01 #define CMD_INV_DEV_ENTRY 0x02 #define CMD_INV_IOMMU_PAGES 0x03 #define CMD_INV_ALL 0x08 #define CMD_COMPL_WAIT_STORE_MASK 0x01 #define CMD_COMPL_WAIT_INT_MASK 0x02 Loading arch/x86/kernel/amd_iommu.c +22 −2 Original line number Diff line number Diff line Loading @@ -463,6 +463,12 @@ static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; } static void build_inv_all(struct iommu_cmd *cmd) { memset(cmd, 0, sizeof(*cmd)); CMD_SET_TYPE(cmd, CMD_INV_ALL); } /* * Writes the command to the IOMMUs command buffer and informs the * hardware about the new command. Loading Loading @@ -567,11 +573,25 @@ static void iommu_flush_tlb_all(struct amd_iommu *iommu) iommu_completion_wait(iommu); } static void iommu_flush_all(struct amd_iommu *iommu) { struct iommu_cmd cmd; build_inv_all(&cmd); iommu_queue_command(iommu, &cmd); iommu_completion_wait(iommu); } void iommu_flush_all_caches(struct amd_iommu *iommu) { if (iommu_feature(iommu, FEATURE_IA)) { iommu_flush_all(iommu); } else { iommu_flush_dte_all(iommu); iommu_flush_tlb_all(iommu); } } /* * Command send function for invalidating a device table entry Loading Loading
arch/x86/include/asm/amd_iommu_types.h +1 −0 Original line number Diff line number Diff line Loading @@ -127,6 +127,7 @@ #define CMD_COMPL_WAIT 0x01 #define CMD_INV_DEV_ENTRY 0x02 #define CMD_INV_IOMMU_PAGES 0x03 #define CMD_INV_ALL 0x08 #define CMD_COMPL_WAIT_STORE_MASK 0x01 #define CMD_COMPL_WAIT_INT_MASK 0x02 Loading
arch/x86/kernel/amd_iommu.c +22 −2 Original line number Diff line number Diff line Loading @@ -463,6 +463,12 @@ static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; } static void build_inv_all(struct iommu_cmd *cmd) { memset(cmd, 0, sizeof(*cmd)); CMD_SET_TYPE(cmd, CMD_INV_ALL); } /* * Writes the command to the IOMMUs command buffer and informs the * hardware about the new command. Loading Loading @@ -567,11 +573,25 @@ static void iommu_flush_tlb_all(struct amd_iommu *iommu) iommu_completion_wait(iommu); } static void iommu_flush_all(struct amd_iommu *iommu) { struct iommu_cmd cmd; build_inv_all(&cmd); iommu_queue_command(iommu, &cmd); iommu_completion_wait(iommu); } void iommu_flush_all_caches(struct amd_iommu *iommu) { if (iommu_feature(iommu, FEATURE_IA)) { iommu_flush_all(iommu); } else { iommu_flush_dte_all(iommu); iommu_flush_tlb_all(iommu); } } /* * Command send function for invalidating a device table entry Loading