Commit 59fb813f authored by Pierre Gondois's avatar Pierre Gondois Committed by Sudeep Holla
Browse files

arm64: dts: Update cache properties for Arm Ltd platforms 



The DeviceTree Specification v0.3 specifies that the cache node
"compatible" and "cache-level" properties are required.

Cf. s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the properties
for unified cache is present ('cache-size', ...).

Update the relevant device trees nodes accordingly.

Signed-off-by: default avatarPierre Gondois <pierre.gondois@arm.com>
Link: https://lore.kernel.org/r/20221107155825.1644604-6-pierre.gondois@arm.com


Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
parent c4a7b9b5

arch/arm64/boot/dts/arm/corstone1000.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ gic: interrupt-controller@1c000000 { 


	L2_0: l2-cache0 {

		compatible = "cache";

		cache-unified;

		cache-level = <2>;

		cache-size = <0x80000>;

		cache-line-size = <64>;

arch/arm64/boot/dts/arm/foundation-v8.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ cpu3: cpu@3 { 


		L2_0: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

		};

	};

arch/arm64/boot/dts/arm/juno-r1.dts

+2 −0
Original line number Diff line number Diff line
@@ -189,6 +189,7 @@ A53_3: cpu@103 { 


		A57_L2: l2-cache0 {

			compatible = "cache";

			cache-unified;

			cache-size = <0x200000>;

			cache-line-size = <64>;

			cache-sets = <2048>;
@@ -197,6 +198,7 @@ A57_L2: l2-cache0 { 


		A53_L2: l2-cache1 {

			compatible = "cache";

			cache-unified;

			cache-size = <0x100000>;

			cache-line-size = <64>;

			cache-sets = <1024>;

arch/arm64/boot/dts/arm/juno-r2.dts

+2 −0
Original line number Diff line number Diff line
@@ -195,6 +195,7 @@ A53_3: cpu@103 { 


		A72_L2: l2-cache0 {

			compatible = "cache";

			cache-unified;

			cache-size = <0x200000>;

			cache-line-size = <64>;

			cache-sets = <2048>;
@@ -203,6 +204,7 @@ A72_L2: l2-cache0 { 


		A53_L2: l2-cache1 {

			compatible = "cache";

			cache-unified;

			cache-size = <0x100000>;

			cache-line-size = <64>;

			cache-sets = <1024>;

arch/arm64/boot/dts/arm/juno.dts

+2 −0
Original line number Diff line number Diff line
@@ -194,6 +194,7 @@ A53_3: cpu@103 { 


		A57_L2: l2-cache0 {

			compatible = "cache";

			cache-unified;

			cache-size = <0x200000>;

			cache-line-size = <64>;

			cache-sets = <2048>;
@@ -202,6 +203,7 @@ A57_L2: l2-cache0 { 


		A53_L2: l2-cache1 {

			compatible = "cache";

			cache-unified;

			cache-size = <0x100000>;

			cache-line-size = <64>;

			cache-sets = <1024>;