Commit 5a4f5be9 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Update free running tigerlake events 

Fix the topic, PMU name, event code and umask.

These updates were generated by:
https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py
with this PR:
https://github.com/intel/perfmon/pull/66



Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20230407001322.2776268-1-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 4781f1f2

tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json

0 → 100644
+50 −0
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",

        "EventCode": "0xff",

        "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",

        "PerPkg": "1",

        "UMask": "0x20",

        "Unit": "imc_free_running_0"

    },

    {

        "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",

        "EventCode": "0xff",

        "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",

        "PerPkg": "1",

        "UMask": "0x10",

        "Unit": "imc_free_running_0"

    },

    {

        "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",

        "EventCode": "0xff",

        "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",

        "PerPkg": "1",

        "UMask": "0x30",

        "Unit": "imc_free_running_0"

    },

    {

        "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",

        "EventCode": "0xff",

        "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",

        "PerPkg": "1",

        "UMask": "0x20",

        "Unit": "imc_free_running_1"

    },

    {

        "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",

        "EventCode": "0xff",

        "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",

        "PerPkg": "1",

        "UMask": "0x10",

        "Unit": "imc_free_running_1"

    },

    {

        "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",

        "EventCode": "0xff",

        "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",

        "PerPkg": "1",

        "UMask": "0x30",

        "Unit": "imc_free_running_1"

    }

]

tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json

+0 −36
Original line number Diff line number Diff line
@@ -93,41 +93,5 @@ 
        "EventName": "UNC_CLOCK.SOCKET",

        "PerPkg": "1",

        "Unit": "CLOCK"

    },

    {

        "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",

        "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",

        "PerPkg": "1",

        "Unit": "imc"

    },

    {

        "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",

        "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",

        "PerPkg": "1",

        "Unit": "imc"

    },

    {

        "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",

        "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",

        "PerPkg": "1",

        "Unit": "imc"

    },

    {

        "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",

        "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",

        "PerPkg": "1",

        "Unit": "imc"

    },

    {

        "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",

        "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",

        "PerPkg": "1",

        "Unit": "imc"

    },

    {

        "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",

        "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",

        "PerPkg": "1",

        "Unit": "imc"

    }

]