Commit 5ac17838 authored by Jonathan Marek's avatar Jonathan Marek Committed by Rob Clark
Browse files

drm/msm/dsi: support CPHY mode for 7nm pll/phy 



Add the required changes to support 7nm pll/phy in CPHY mode.

This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.

Signed-off-by: default avatarJonathan Marek <jonathan@marek.ca>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210617144349.28448-4-jonathan@marek.ca


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent bb5b94f5

drivers/gpu/drm/msm/dsi/dsi_host.c

+30 −4
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ 
#include "dsi_cfg.h"

#include "msm_kms.h"

#include "msm_gem.h"

#include "phy/dsi_phy.h"



#define DSI_RESET_TOGGLE_DELAY_MS 20
@@ -167,6 +168,9 @@ struct msm_dsi_host { 
	int dlane_swap;

	int num_data_lanes;



	/* from phy DT */

	bool cphy_mode;



	u32 dma_cmd_ctrl_restore;



	bool registered;
@@ -510,6 +514,7 @@ int msm_dsi_runtime_resume(struct device *dev) 


int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)

{

	u32 byte_intf_rate;

	int ret;



	DBG("Set clk rates: pclk=%d, byteclk=%d",
@@ -529,8 +534,13 @@ int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) 
	}



	if (msm_host->byte_intf_clk) {

		ret = clk_set_rate(msm_host->byte_intf_clk,

				   msm_host->byte_clk_rate / 2);

		/* For CPHY, byte_intf_clk is same as byte_clk */

		if (msm_host->cphy_mode)

			byte_intf_rate = msm_host->byte_clk_rate;

		else

			byte_intf_rate = msm_host->byte_clk_rate / 2;



		ret = clk_set_rate(msm_host->byte_intf_clk, byte_intf_rate);

		if (ret) {

			pr_err("%s: Failed to set rate byte intf clk, %d\n",

			       __func__, ret);
@@ -710,6 +720,10 @@ static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_dual_dsi) 
		lanes = 1;

	}



	/* CPHY "byte_clk" is in units of 16 bits */

	if (msm_host->cphy_mode)

		do_div(pclk_bpp, (16 * lanes));

	else

		do_div(pclk_bpp, (8 * lanes));



	msm_host->pixel_clk_rate = pclk_rate;
@@ -936,6 +950,9 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, 
	data |= DSI_CTRL_ENABLE;



	dsi_write(msm_host, REG_DSI_CTRL, data);



	if (msm_host->cphy_mode)

		dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));

}



static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi)
@@ -2226,6 +2243,8 @@ int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, 
	struct clk *byte_clk_provider, *pixel_clk_provider;

	int ret;



	msm_host->cphy_mode = src_phy->cphy_mode;



	ret = msm_dsi_phy_get_clk_provider(src_phy,

				&byte_clk_provider, &pixel_clk_provider);

	if (ret) {
@@ -2297,6 +2316,13 @@ void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, 
		return;

	}



	/* CPHY transmits 16 bits over 7 clock cycles

	 * "byte_clk" is in units of 16-bits (see dsi_calc_pclk),

	 * so multiply by 7 to get the "bitclk rate"

	 */

	if (msm_host->cphy_mode)

		clk_req->bitclk_rate = msm_host->byte_clk_rate * 7;

	else

		clk_req->bitclk_rate = msm_host->byte_clk_rate * 8;

	clk_req->escclk_rate = msm_host->esc_clk_rate;

}

drivers/gpu/drm/msm/dsi/phy/dsi_phy.c

+49 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 


#include <linux/clk-provider.h>

#include <linux/platform_device.h>

#include <dt-bindings/phy/phy.h>



#include "dsi_phy.h"
@@ -461,6 +462,51 @@ int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, 
	return 0;

}



int msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,

	struct msm_dsi_phy_clk_request *clk_req)

{

	const unsigned long bit_rate = clk_req->bitclk_rate;

	const unsigned long esc_rate = clk_req->escclk_rate;

	s32 ui, ui_x7;

	s32 tmax, tmin;

	s32 coeff = 1000; /* Precision, should avoid overflow */

	s32 temp;



	if (!bit_rate || !esc_rate)

		return -EINVAL;



	ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);

	ui_x7 = ui * 7;



	temp = S_DIV_ROUND_UP(38 * coeff, ui_x7);

	tmin = max_t(s32, temp, 0);

	temp = (95 * coeff) / ui_x7;

	tmax = max_t(s32, temp, 0);

	timing->clk_prepare = linear_inter(tmax, tmin, 50, 0, false);



	tmin = DIV_ROUND_UP(50 * coeff, ui_x7);

	tmax = 255;

	timing->hs_rqst = linear_inter(tmax, tmin, 1, 0, false);



	tmin = DIV_ROUND_UP(100 * coeff, ui_x7) - 1;

	tmax = 255;

	timing->hs_exit = linear_inter(tmax, tmin, 10, 0, false);



	tmin = 1;

	tmax = 32;

	timing->shared_timings.clk_post = linear_inter(tmax, tmin, 80, 0, false);



	tmin = min_t(s32, 64, S_DIV_ROUND_UP(262 * coeff, ui_x7) - 1);

	tmax = 64;

	timing->shared_timings.clk_pre = linear_inter(tmax, tmin, 20, 0, false);



	DBG("%d, %d, %d, %d, %d",

		timing->shared_timings.clk_pre, timing->shared_timings.clk_post,

		timing->clk_prepare, timing->hs_exit, timing->hs_rqst);



	return 0;

}



static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)

{

	struct regulator_bulk_data *s = phy->supplies;
@@ -626,6 +672,7 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) 
	struct msm_dsi_phy *phy;

	struct device *dev = &pdev->dev;

	const struct of_device_id *match;

	u32 phy_type;

	int ret;



	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
@@ -657,6 +704,8 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) 


	phy->regulator_ldo_mode = of_property_read_bool(dev->of_node,

				"qcom,dsi-phy-regulator-ldo-mode");

	if (!of_property_read_u32(dev->of_node, "phy-type", &phy_type))

		phy->cphy_mode = (phy_type == PHY_TYPE_CPHY);



	phy->base = msm_ioremap_size(pdev, "dsi_phy", "DSI_PHY", &phy->base_size);

	if (IS_ERR(phy->base)) {

drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

+3 −0
Original line number Diff line number Diff line
@@ -99,6 +99,7 @@ struct msm_dsi_phy { 


	enum msm_dsi_phy_usecase usecase;

	bool regulator_ldo_mode;

	bool cphy_mode;



	struct clk_hw *vco_hw;

	bool pll_on;
@@ -119,5 +120,7 @@ int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing, 
				struct msm_dsi_phy_clk_request *clk_req);

int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,

				struct msm_dsi_phy_clk_request *clk_req);

int msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,

				struct msm_dsi_phy_clk_request *clk_req);



#endif /* __DSI_PHY_H__ */

drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c

+102 −43
Original line number Diff line number Diff line
@@ -256,7 +256,7 @@ static void dsi_pll_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *confi 
		  (config->frac_div_start & 0x30000) >> 16);

	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40);

	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);

	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO: 0x00 for CPHY */

	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, pll->phy->cphy_mode ? 0x00 : 0x10);

	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, config->pll_clock_inverters);

}
@@ -642,7 +642,8 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide 


	/* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */

	hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,

					  CLK_SET_RATE_PARENT, 1, 8);

					  CLK_SET_RATE_PARENT, 1,

					  pll_7nm->phy->cphy_mode ? 7 : 8);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

		goto fail;
@@ -663,13 +664,26 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide 
	snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id);

	snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);



	hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,

					  0, 1, 4);

	if (pll_7nm->phy->cphy_mode)

		hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 2, 7);

	else

		hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 4);

	if (IS_ERR(hw)) {

		ret = PTR_ERR(hw);

		goto fail;

	}



	/* in CPHY mode, pclk_mux will always have post_out_div as parent

	 * don't register a pclk_mux clock and just use post_out_div instead

	 */

	if (pll_7nm->phy->cphy_mode) {

		u32 data;



		data = dsi_phy_read(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);

		dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data | 3);



		snprintf(parent, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id);

	} else {

		snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->phy->id);

		snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);

		snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id);
@@ -687,8 +701,10 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide 
			goto fail;

		}



	snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->phy->id);

		snprintf(parent, 32, "dsi%d_pclk_mux", pll_7nm->phy->id);

	}



	snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->phy->id);



	/* PIX CLK DIV : DIV_CTRL_7_4*/

	hw = devm_clk_hw_register_divider(dev, clk_name, parent,
@@ -813,15 +829,21 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, 
	struct msm_dsi_dphy_timing *timing = &phy->timing;

	void __iomem *base = phy->base;

	bool less_than_1500_mhz;

	u32 vreg_ctrl_0, glbl_str_swi_cal_sel_ctrl, glbl_hstx_str_ctrl_0;

	u32 vreg_ctrl_0, vreg_ctrl_1, lane_ctrl0;

	u32 glbl_pemph_ctrl_0;

	u32 glbl_str_swi_cal_sel_ctrl, glbl_hstx_str_ctrl_0;

	u32 glbl_rescode_top_ctrl, glbl_rescode_bot_ctrl;

	u32 data;



	DBG("");



	if (msm_dsi_dphy_timing_calc_v4(timing, clk_req)) {

	if (phy->cphy_mode)

		ret = msm_dsi_cphy_timing_calc_v4(timing, clk_req);

	else

		ret = msm_dsi_dphy_timing_calc_v4(timing, clk_req);

	if (ret) {

		DRM_DEV_ERROR(&phy->pdev->dev,

			"%s: D-PHY timing calculation failed\n", __func__);

			"%s: PHY timing calculation failed\n", __func__);

		return -EINVAL;

	}
@@ -842,6 +864,10 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, 
	/* Alter PHY configurations if data rate less than 1.5GHZ*/

	less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000);



	/* For C-PHY, no low power settings for lower clk rate */

	if (phy->cphy_mode)

		less_than_1500_mhz = false;



	if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {

		vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;

		glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d :  0x00;
@@ -856,6 +882,17 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, 
		glbl_rescode_bot_ctrl = 0x3c;

	}



	if (phy->cphy_mode) {

		vreg_ctrl_0 = 0x51;

		vreg_ctrl_1 = 0x55;

		glbl_pemph_ctrl_0 = 0x11;

		lane_ctrl0 = 0x17;

	} else {

		vreg_ctrl_1 = 0x5c;

		glbl_pemph_ctrl_0 = 0x00;

		lane_ctrl0 = 0x1f;

	}



	/* de-assert digital and pll power down */

	data = BIT(6) | BIT(5);

	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data);
@@ -876,15 +913,22 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, 
	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG0, 0x21);

	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG1, 0x84);



	if (phy->cphy_mode)

		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_CTRL, BIT(6));



	/* Enable LDO */

	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_0, vreg_ctrl_0);

	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_1, 0x5c);

	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_1, vreg_ctrl_1);



	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x00);

	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL,

		      glbl_str_swi_cal_sel_ctrl);

	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0,

		      glbl_hstx_str_ctrl_0);

	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0, 0x00);

	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0,

		      glbl_pemph_ctrl_0);

	if (phy->cphy_mode)

		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1, 0x01);

	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL,

		      glbl_rescode_top_ctrl);

	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL,
@@ -894,9 +938,10 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, 
	/* Remove power down from all blocks */

	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x7f);



	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, 0x1f);

	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, lane_ctrl0);



	/* Select full-rate mode */

	if (!phy->cphy_mode)

		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_2, 0x40);



	ret = dsi_7nm_set_usecase(phy);
@@ -907,6 +952,19 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, 
	}



	/* DSI PHY timings */

	if (phy->cphy_mode) {

		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0, 0x00);

		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4, timing->hs_exit);

		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5,

			timing->shared_timings.clk_pre);

		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6, timing->clk_prepare);

		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7,

			timing->shared_timings.clk_post);

		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8, timing->hs_rqst);

		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9, 0x02);

		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10, 0x04);

		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11, 0x00);

	} else {

		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0, 0x00);

		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1, timing->clk_zero);

		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2, timing->clk_prepare);
@@ -923,6 +981,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, 
			timing->shared_timings.clk_pre);

		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13,

			timing->shared_timings.clk_post);

	}



	/* DSI lane settings */

	dsi_phy_hw_v4_0_lane_settings(phy);