Commit 5eb82ddb authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Bjorn Andersson
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ARM: dts: qcom: align SDHCI reg-names with DT schema 



DT schema requires SDHCI reg names to be hc/core without "_mem" suffix,
just like TXT bindings were expecting before the conversion.

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarDouglas Anderson <dianders@chromium.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220712144245.17417-5-krzysztof.kozlowski@linaro.org
parent 2e312b34

arch/arm/boot/dts/qcom-apq8084.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -422,7 +422,7 @@ blsp2_uart2: serial@f995e000 { 
		mmc@f9824900 {

			compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";

			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;

			reg-names = "hc_mem", "core_mem";

			reg-names = "hc", "core";

			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
@@ -435,7 +435,7 @@ mmc@f9824900 { 
		mmc@f98a4900 {

			compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";

			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;

			reg-names = "hc_mem", "core_mem";

			reg-names = "hc", "core";

			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC2_APPS_CLK>,

arch/arm/boot/dts/qcom-ipq4019.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -224,6 +224,7 @@ vqmmc: regulator@1948000 { 
		sdhci: mmc@7824900 {

			compatible = "qcom,sdhci-msm-v4";

			reg = <0x7824900 0x11c>, <0x7824000 0x800>;

			reg-names = "hc", "core";

			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

			bus-width = <8>;

arch/arm/boot/dts/qcom-msm8226.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -130,7 +130,7 @@ apcs: syscon@f9011000 { 
		sdhc_1: mmc@f9824900 {

			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";

			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;

			reg-names = "hc_mem", "core_mem";

			reg-names = "hc", "core";

			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";
@@ -146,7 +146,7 @@ sdhc_1: mmc@f9824900 { 
		sdhc_2: mmc@f98a4900 {

			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";

			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;

			reg-names = "hc_mem", "core_mem";

			reg-names = "hc", "core";

			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";
@@ -162,7 +162,7 @@ sdhc_2: mmc@f98a4900 { 
		sdhc_3: mmc@f9864900 {

			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";

			reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;

			reg-names = "hc_mem", "core_mem";

			reg-names = "hc", "core";

			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

arch/arm/boot/dts/qcom-msm8974.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -439,7 +439,7 @@ acc3: clock-controller@f90b8000 { 
		sdhc_1: mmc@f9824900 {

			compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";

			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;

			reg-names = "hc_mem", "core_mem";

			reg-names = "hc", "core";

			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";
@@ -456,7 +456,7 @@ sdhc_1: mmc@f9824900 { 
		sdhc_3: mmc@f9864900 {

			compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";

			reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;

			reg-names = "hc_mem", "core_mem";

			reg-names = "hc", "core";

			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";
@@ -475,7 +475,7 @@ sdhc_3: mmc@f9864900 { 
		sdhc_2: mmc@f98a4900 {

			compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";

			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;

			reg-names = "hc_mem", "core_mem";

			reg-names = "hc", "core";

			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

arch/arm/boot/dts/qcom-sdx65.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -334,7 +334,7 @@ glink-edge { 
		sdhc_1: mmc@8804000 {

			compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";

			reg = <0x08804000 0x1000>;

			reg-names = "hc_mem";

			reg-names = "hc";

			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";