Commit 5edf8bd6 authored by Niklas Söderlund's avatar Niklas Söderlund Committed by Geert Uytterhoeven
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arm64: dts: renesas: rcar-gen3: Add missing CMT nodes 



Add device nodes for the Compare Match Timer (CMT) on the Renesas R-Car
M3-W+ (r8a77961) and D3 (r8a77995) SoCs.

Signed-off-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20201209200738.811173-2-niklas.soderlund+renesas@ragnatech.se


[geert: squashed two commits]
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 5c8fe583

arch/arm64/boot/dts/renesas/r8a77961.dtsi

+70 −0
Original line number Diff line number Diff line
@@ -453,6 +453,76 @@ pfc: pinctrl@e6060000 { 
			reg = <0 0xe6060000 0 0x50c>;

		};



		cmt0: timer@e60f0000 {

			compatible = "renesas,r8a77961-cmt0",

				     "renesas,rcar-gen3-cmt0";

			reg = <0 0xe60f0000 0 0x1004>;

			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 303>;

			clock-names = "fck";

			power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;

			resets = <&cpg 303>;

			status = "disabled";

		};



		cmt1: timer@e6130000 {

			compatible = "renesas,r8a77961-cmt1",

				     "renesas,rcar-gen3-cmt1";

			reg = <0 0xe6130000 0 0x1004>;

			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 302>;

			clock-names = "fck";

			power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;

			resets = <&cpg 302>;

			status = "disabled";

		};



		cmt2: timer@e6140000 {

			compatible = "renesas,r8a77961-cmt1",

				     "renesas,rcar-gen3-cmt1";

			reg = <0 0xe6140000 0 0x1004>;

			interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 301>;

			clock-names = "fck";

			power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;

			resets = <&cpg 301>;

			status = "disabled";

		};



		cmt3: timer@e6148000 {

			compatible = "renesas,r8a77961-cmt1",

				     "renesas,rcar-gen3-cmt1";

			reg = <0 0xe6148000 0 0x1004>;

			interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 300>;

			clock-names = "fck";

			power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;

			resets = <&cpg 300>;

			status = "disabled";

		};



		cpg: clock-controller@e6150000 {

			compatible = "renesas,r8a77961-cpg-mssr";

			reg = <0 0xe6150000 0 0x1000>;

arch/arm64/boot/dts/renesas/r8a77995.dtsi

+70 −0
Original line number Diff line number Diff line
@@ -193,6 +193,76 @@ pfc: pinctrl@e6060000 { 
			reg = <0 0xe6060000 0 0x508>;

		};



		cmt0: timer@e60f0000 {

			compatible = "renesas,r8a77995-cmt0",

				     "renesas,rcar-gen3-cmt0";

			reg = <0 0xe60f0000 0 0x1004>;

			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 303>;

			clock-names = "fck";

			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;

			resets = <&cpg 303>;

			status = "disabled";

		};



		cmt1: timer@e6130000 {

			compatible = "renesas,r8a77995-cmt1",

				     "renesas,rcar-gen3-cmt1";

			reg = <0 0xe6130000 0 0x1004>;

			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 302>;

			clock-names = "fck";

			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;

			resets = <&cpg 302>;

			status = "disabled";

		};



		cmt2: timer@e6140000 {

			compatible = "renesas,r8a77995-cmt1",

				     "renesas,rcar-gen3-cmt1";

			reg = <0 0xe6140000 0 0x1004>;

			interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 301>;

			clock-names = "fck";

			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;

			resets = <&cpg 301>;

			status = "disabled";

		};



		cmt3: timer@e6148000 {

			compatible = "renesas,r8a77995-cmt1",

				     "renesas,rcar-gen3-cmt1";

			reg = <0 0xe6148000 0 0x1004>;

			interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 300>;

			clock-names = "fck";

			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;

			resets = <&cpg 300>;

			status = "disabled";

		};



		cpg: clock-controller@e6150000 {

			compatible = "renesas,r8a77995-cpg-mssr";

			reg = <0 0xe6150000 0 0x1000>;