Commit 60a2e9ee authored by James Zhu's avatar James Zhu Committed by Alex Deucher
Browse files

drm/amdgpu/vcn: add common vcn sofware ring decode 



Add common vcn sofware ring decode.

v2: fixed compiling error

Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Reviewed-by: default avatarChristian Koenig <Christian.Koenig@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e02fe3bc

drivers/gpu/drm/amd/amdgpu/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -167,6 +167,7 @@ amdgpu-y += \ 
# add VCN and JPEG block

amdgpu-y += \

	amdgpu_vcn.o \

	vcn_sw_ring.o \

	vcn_v1_0.o \

	vcn_v2_0.o \

	vcn_v2_5.o \

drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.c

0 → 100644
+85 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2022 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#include "amdgpu.h"



void vcn_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,

	u64 seq, uint32_t flags)

{

	WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);



	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE);

	amdgpu_ring_write(ring, addr);

	amdgpu_ring_write(ring, upper_32_bits(addr));

	amdgpu_ring_write(ring, seq);

	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP);

}



void vcn_dec_sw_ring_insert_end(struct amdgpu_ring *ring)

{

	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);

}



void vcn_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,

	struct amdgpu_ib *ib, uint32_t flags)

{

	uint32_t vmid = AMDGPU_JOB_GET_VMID(job);



	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB);

	amdgpu_ring_write(ring, vmid);

	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));

	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

	amdgpu_ring_write(ring, ib->length_dw);

}



void vcn_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

	uint32_t val, uint32_t mask)

{

	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT);

	amdgpu_ring_write(ring, reg << 2);

	amdgpu_ring_write(ring, mask);

	amdgpu_ring_write(ring, val);

}



void vcn_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,

	uint32_t vmid, uint64_t pd_addr)

{

	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];

	uint32_t data0, data1, mask;



	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);



	/* wait for register write */

	data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;

	data1 = lower_32_bits(pd_addr);

	mask = 0xffffffff;

	vcn_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask);

}



void vcn_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,

	uint32_t val)

{

	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE);

	amdgpu_ring_write(ring,	reg << 2);

	amdgpu_ring_write(ring, val);

}

drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.h

0 → 100644
+44 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2022 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef __VCN_SW_RING_H__

#define __VCN_SW_RING_H__



#define VCN_SW_RING_EMIT_FRAME_SIZE \

		(4 + /* vcn_dec_sw_ring_emit_vm_flush */ \

		5 + 5 + /* vcn_dec_sw_ring_emit_fence x2 vm fence */ \

		1) /* vcn_dec_sw_ring_insert_end */



void vcn_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,

	u64 seq, uint32_t flags);

void vcn_dec_sw_ring_insert_end(struct amdgpu_ring *ring);

void vcn_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,

	struct amdgpu_ib *ib, uint32_t flags);

void vcn_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

	uint32_t val, uint32_t mask);

void vcn_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,

	uint32_t vmid, uint64_t pd_addr);

void vcn_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,

	uint32_t val);



#endif /* __VCN_SW_RING_H__ */