Commit 61299e18 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

Merge branch irq/misc-5.19 into irq/irqchip-next 



* irq/misc-5.19:
  : .
  : Misc fixes and minor improvements:
  :
  : - GIC: Improve warning when the firmware tables are inconsistent
  :
  : - csky: Use true/false as boolean litterals
  :
  : - imx-irqsteer: Add runtime PM support
  :
  : - armada-370-xp: Enable CPU affinity for MSIs, avoid messing with
  :   PMU interrupts on some variants
  :
  : - aspeed: Fix handling of irq_of_parse_and_map() errors
  :
  : - sun6i: Fix sparse warnings
  :
  : - xtensa-mx: Fix initial IRQ affinity in non-SMP setup
  :
  : - exiu: Fix acknowledgment of edge-triggered interrupts
  :
  : - sunxi: Generalise configuration for further reuse
  : .
  irqchip: Add Kconfig symbols for sunxi drivers
  irqchip/armada-370-xp: Do not touch Performance Counter Overflow on A375, A38x, A39x
  irqchip/gic: Improved warning about incorrect type
  irqchip/csky: Return true/false (not 1/0) from bool functions
  irqchip/imx-irqsteer: Add runtime PM support
  irqchip/imx-irqsteer: Constify irq_chip struct
  irqchip/armada-370-xp: Enable MSI affinity configuration
  irqchip/aspeed-scu-ic: Fix irq_of_parse_and_map() return value
  irqchip/aspeed-i2c-ic: Fix irq_of_parse_and_map() return value
  irqchip/sun6i-r: Use NULL for chip_data
  irqchip/xtensa-mx: Fix initial IRQ affinity in non-SMP setup
  irqchip/exiu: Fix acknowledgment of edge triggered interrupts

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parents a6ad8551 d421fd6d

arch/arm/mach-sunxi/Kconfig

+9 −3
Original line number Diff line number Diff line
@@ -4,10 +4,7 @@ menuconfig ARCH_SUNXI 
	depends on ARCH_MULTI_V5 || ARCH_MULTI_V7

	select ARCH_HAS_RESET_CONTROLLER

	select CLKSRC_MMIO

	select GENERIC_IRQ_CHIP

	select GPIOLIB

	select IRQ_DOMAIN_HIERARCHY

	select IRQ_FASTEOI_HIERARCHY_HANDLERS

	select PINCTRL

	select PM_OPP

	select SUN4I_TIMER
@@ -22,10 +19,12 @@ if ARCH_MULTI_V7 
config MACH_SUN4I

	bool "Allwinner A10 (sun4i) SoCs support"

	default ARCH_SUNXI

	select SUN4I_INTC



config MACH_SUN5I

	bool "Allwinner A10s / A13 (sun5i) SoCs support"

	default ARCH_SUNXI

	select SUN4I_INTC

	select SUN5I_HSTIMER



config MACH_SUN6I
@@ -34,6 +33,8 @@ config MACH_SUN6I 
	select ARM_GIC

	select MFD_SUN6I_PRCM

	select SUN5I_HSTIMER

	select SUN6I_R_INTC

	select SUNXI_NMI_INTC



config MACH_SUN7I

	bool "Allwinner A20 (sun7i) SoCs support"
@@ -43,17 +44,21 @@ config MACH_SUN7I 
	select ARCH_SUPPORTS_BIG_ENDIAN

	select HAVE_ARM_ARCH_TIMER

	select SUN5I_HSTIMER

	select SUNXI_NMI_INTC



config MACH_SUN8I

	bool "Allwinner sun8i Family SoCs support"

	default ARCH_SUNXI

	select ARM_GIC

	select MFD_SUN6I_PRCM

	select SUN6I_R_INTC

	select SUNXI_NMI_INTC



config MACH_SUN9I

	bool "Allwinner (sun9i) SoCs support"

	default ARCH_SUNXI

	select ARM_GIC

	select SUNXI_NMI_INTC



config ARCH_SUNXI_MC_SMP

	bool
@@ -69,6 +74,7 @@ if ARCH_MULTI_V5 
config MACH_SUNIV

	bool "Allwinner ARMv5 F-series (suniv) SoCs support"

	default ARCH_SUNXI

	select SUN4I_INTC

	help

	  Support for Allwinner suniv ARMv5 SoCs.

	  (F1C100A, F1C100s, F1C200s, F1C500, F1C600)

arch/arm64/Kconfig.platforms

+3 −3
Original line number Diff line number Diff line
@@ -11,12 +11,11 @@ config ARCH_ACTIONS 
config ARCH_SUNXI

	bool "Allwinner sunxi 64-bit SoC Family"

	select ARCH_HAS_RESET_CONTROLLER

	select GENERIC_IRQ_CHIP

	select IRQ_DOMAIN_HIERARCHY

	select IRQ_FASTEOI_HIERARCHY_HANDLERS

	select PINCTRL

	select RESET_CONTROLLER

	select SUN4I_TIMER

	select SUN6I_R_INTC

	select SUNXI_NMI_INTC

	help

	  This enables support for Allwinner sunxi based SoCs like the A64.
@@ -253,6 +252,7 @@ config ARCH_INTEL_SOCFPGA 


config ARCH_SYNQUACER

	bool "Socionext SynQuacer SoC Family"

	select IRQ_FASTEOI_HIERARCHY_HANDLERS



config ARCH_TEGRA

	bool "NVIDIA Tegra SoC Family"

drivers/irqchip/Kconfig

+12 −0
Original line number Diff line number Diff line
@@ -257,6 +257,18 @@ config ST_IRQCHIP 
	help

	  Enables SysCfg Controlled IRQs on STi based platforms.



config SUN4I_INTC

	bool



config SUN6I_R_INTC

	bool

	select IRQ_DOMAIN_HIERARCHY

	select IRQ_FASTEOI_HIERARCHY_HANDLERS



config SUNXI_NMI_INTC

	bool

	select GENERIC_IRQ_CHIP



config TB10X_IRQC

	bool

	select IRQ_DOMAIN

drivers/irqchip/Makefile

+3 −3
Original line number Diff line number Diff line
@@ -23,9 +23,9 @@ obj-$(CONFIG_OMPIC) += irq-ompic.o 
obj-$(CONFIG_OR1K_PIC)			+= irq-or1k-pic.o

obj-$(CONFIG_ORION_IRQCHIP)		+= irq-orion.o

obj-$(CONFIG_OMAP_IRQCHIP)		+= irq-omap-intc.o

obj-$(CONFIG_ARCH_SUNXI)		+= irq-sun4i.o

obj-$(CONFIG_ARCH_SUNXI)		+= irq-sun6i-r.o

obj-$(CONFIG_ARCH_SUNXI)		+= irq-sunxi-nmi.o

obj-$(CONFIG_SUN4I_INTC)		+= irq-sun4i.o

obj-$(CONFIG_SUN6I_R_INTC)		+= irq-sun6i-r.o

obj-$(CONFIG_SUNXI_NMI_INTC)		+= irq-sunxi-nmi.o

obj-$(CONFIG_ARCH_SPEAR3XX)		+= spear-shirq.o

obj-$(CONFIG_ARM_GIC)			+= irq-gic.o irq-gic-common.o

obj-$(CONFIG_ARM_GIC_PM)		+= irq-gic-pm.o

drivers/irqchip/irq-armada-370-xp.c

+43 −13
Original line number Diff line number Diff line
@@ -209,15 +209,29 @@ static struct msi_domain_info armada_370_xp_msi_domain_info = { 


static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)

{

	unsigned int cpu = cpumask_first(irq_data_get_effective_affinity_mask(data));



	msg->address_lo = lower_32_bits(msi_doorbell_addr);

	msg->address_hi = upper_32_bits(msi_doorbell_addr);

	msg->data = 0xf00 | (data->hwirq + PCI_MSI_DOORBELL_START);

	msg->data = BIT(cpu + 8) | (data->hwirq + PCI_MSI_DOORBELL_START);

}



static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data,

					  const struct cpumask *mask, bool force)

{

	unsigned int cpu;



	if (!force)

		cpu = cpumask_any_and(mask, cpu_online_mask);

	else

		cpu = cpumask_first(mask);



	if (cpu >= nr_cpu_ids)

		return -EINVAL;



	irq_data_update_effective_affinity(irq_data, cpumask_of(cpu));



	return IRQ_SET_MASK_OK;

}



static struct irq_chip armada_370_xp_msi_bottom_irq_chip = {
@@ -264,11 +278,21 @@ static const struct irq_domain_ops armada_370_xp_msi_domain_ops = { 
	.free	= armada_370_xp_msi_free,

};



static int armada_370_xp_msi_init(struct device_node *node,

				  phys_addr_t main_int_phys_base)

static void armada_370_xp_msi_reenable_percpu(void)

{

	u32 reg;



	/* Enable MSI doorbell mask and combined cpu local interrupt */

	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)

		| PCI_MSI_DOORBELL_MASK;

	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);

	/* Unmask local doorbell interrupt */

	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);

}



static int armada_370_xp_msi_init(struct device_node *node,

				  phys_addr_t main_int_phys_base)

{

	msi_doorbell_addr = main_int_phys_base +

		ARMADA_370_XP_SW_TRIG_INT_OFFS;
@@ -287,18 +311,13 @@ static int armada_370_xp_msi_init(struct device_node *node, 
		return -ENOMEM;

	}



	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)

		| PCI_MSI_DOORBELL_MASK;



	writel(reg, per_cpu_int_base +

	       ARMADA_370_XP_IN_DRBEL_MSK_OFFS);



	/* Unmask IPI interrupt */

	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);

	armada_370_xp_msi_reenable_percpu();



	return 0;

}

#else

static void armada_370_xp_msi_reenable_percpu(void) {}



static inline int armada_370_xp_msi_init(struct device_node *node,

					 phys_addr_t main_int_phys_base)

{
@@ -308,7 +327,16 @@ static inline int armada_370_xp_msi_init(struct device_node *node, 


static void armada_xp_mpic_perf_init(void)

{

	unsigned long cpuid = cpu_logical_map(smp_processor_id());

	unsigned long cpuid;



	/*

	 * This Performance Counter Overflow interrupt is specific for

	 * Armada 370 and XP. It is not available on Armada 375, 38x and 39x.

	 */

	if (!of_machine_is_compatible("marvell,armada-370-xp"))

		return;



	cpuid = cpu_logical_map(smp_processor_id());



	/* Enable Performance Counter Overflow interrupts */

	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
@@ -501,6 +529,8 @@ static void armada_xp_mpic_reenable_percpu(void) 
	}



	ipi_resume();



	armada_370_xp_msi_reenable_percpu();

}



static int armada_xp_mpic_starting_cpu(unsigned int cpu)