Commit 618682b3 authored by Richard Schleich's avatar Richard Schleich Committed by Florian Fainelli
Browse files

ARM: dts: bcm2711: Add the missing L1/L2 cache information 



This patch fixes the kernel warning
"cacheinfo: Unable to detect cache hierarchy for CPU 0"
for the bcm2711 on newer kernel versions.

Signed-off-by: default avatarRichard Schleich <rs@noreya.tech>
Tested-by: default avatarStefan Wahren <stefan.wahren@i2se.com>
[florian: Align and remove comments matching property values]
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
parent bdf8762d

arch/arm/boot/dts/bcm2711.dtsi

+50 −0
Original line number Diff line number Diff line
@@ -458,12 +458,26 @@ cpus: cpus { 
		#size-cells = <0>;

		enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit



		/* Source for d/i-cache-line-size and d/i-cache-sets

		 * https://developer.arm.com/documentation/100095/0003

		 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en

		 * Source for d/i-cache-size

		 * https://www.raspberrypi.com/documentation/computers

		 * /processors.html#bcm2711

		 */

		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a72";

			reg = <0>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x000000d8>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set

			next-level-cache = <&l2>;

		};



		cpu1: cpu@1 {
@@ -472,6 +486,13 @@ cpu1: cpu@1 { 
			reg = <1>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x000000e0>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set

			next-level-cache = <&l2>;

		};



		cpu2: cpu@2 {
@@ -480,6 +501,13 @@ cpu2: cpu@2 { 
			reg = <2>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x000000e8>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set

			next-level-cache = <&l2>;

		};



		cpu3: cpu@3 {
@@ -488,6 +516,28 @@ cpu3: cpu@3 { 
			reg = <3>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x000000f0>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set

			next-level-cache = <&l2>;

		};



		/* Source for d/i-cache-line-size and d/i-cache-sets

		 *  https://developer.arm.com/documentation/100095/0003

		 *  /Level-2-Memory-System/About-the-L2-memory-system?lang=en

		 *  Source for d/i-cache-size

		 *  https://www.raspberrypi.com/documentation/computers

		 *  /processors.html#bcm2711

		 */

		l2: l2-cache0 {

			compatible = "cache";

			cache-size = <0x100000>;

			cache-line-size = <64>;

			cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set

			cache-level = <2>;

		};

	};