Commit 63c0bf99 authored by George Shen's avatar George Shen Committed by Alex Deucher
Browse files

drm/amd/display: Add link encoding to timing BW calculation parameters 



[Why]
There certain cases where the timing BW is dependent on the type of link
encoding in use. Thus to calculate the correct BW required for a given
timing, the link encoding should be added as a parameter.

Reviewed-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Acked-by: default avatarAlan Liu <haoping.liu@amd.com>
Signed-off-by: default avatarGeorge Shen <george.shen@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 97476418

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+7 −1
Original line number Diff line number Diff line
@@ -5793,6 +5793,7 @@ static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, 
				edp_min_bpp_x16, edp_max_bpp_x16,

				dsc_caps,

				&stream->timing,

				dc_link_get_highest_encoding_format(aconnector->dc_link),

				&bw_range)) {



		if (bw_range.max_kbps < link_bw_in_kbps) {
@@ -5801,6 +5802,7 @@ static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, 
					&dsc_options,

					0,

					&stream->timing,

					dc_link_get_highest_encoding_format(aconnector->dc_link),

					&dsc_cfg)) {

				stream->timing.dsc_cfg = dsc_cfg;

				stream->timing.flags.DSC = 1;
@@ -5815,6 +5817,7 @@ static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, 
				&dsc_options,

				link_bw_in_kbps,

				&stream->timing,

				dc_link_get_highest_encoding_format(aconnector->dc_link),

				&dsc_cfg)) {

		stream->timing.dsc_cfg = dsc_cfg;

		stream->timing.flags.DSC = 1;
@@ -5858,12 +5861,14 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, 
						&dsc_options,

						link_bandwidth_kbps,

						&stream->timing,

						dc_link_get_highest_encoding_format(aconnector->dc_link),

						&stream->timing.dsc_cfg)) {

				stream->timing.flags.DSC = 1;

				DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);

			}

		} else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {

			timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);

			timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,

					dc_link_get_highest_encoding_format(aconnector->dc_link));

			max_supported_bw_in_kbps = link_bandwidth_kbps;

			dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
@@ -5875,6 +5880,7 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, 
						&dsc_options,

						dsc_max_supported_bw_in_kbps,

						&stream->timing,

						dc_link_get_highest_encoding_format(aconnector->dc_link),

						&stream->timing.dsc_cfg)) {

					stream->timing.flags.DSC = 1;

					DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

+10 −4
Original line number Diff line number Diff line
@@ -828,6 +828,7 @@ static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *p 
					&dsc_options,

					0,

					params[i].timing,

					dc_link_get_highest_encoding_format(params[i].aconnector->dc_link),

					&params[i].timing->dsc_cfg)) {

			params[i].timing->flags.DSC = 1;
@@ -878,7 +879,9 @@ static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn) 
			param.sink->ctx->dc->res_pool->dscs[0],

			&param.sink->dsc_caps.dsc_dec_caps,

			&dsc_options,

			(int) kbps, param.timing, &dsc_config);

			(int) kbps, param.timing,

			dc_link_get_highest_encoding_format(param.aconnector->dc_link),

			&dsc_config);



	return dsc_config.bits_per_pixel;

}
@@ -1116,8 +1119,11 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, 
				dsc_policy.min_target_bpp * 16,

				dsc_policy.max_target_bpp * 16,

				&stream->sink->dsc_caps.dsc_dec_caps,

				&stream->timing, &params[count].bw_range))

			params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);

				&stream->timing,

				dc_link_get_highest_encoding_format(dc_link),

				&params[count].bw_range))

			params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,

					dc_link_get_highest_encoding_format(dc_link));



		count++;

	}
@@ -1577,7 +1583,7 @@ static bool is_dsc_common_config_possible(struct dc_stream_state *stream, 
				       dsc_policy.min_target_bpp * 16,

				       dsc_policy.max_target_bpp * 16,

				       &stream->sink->dsc_caps.dsc_dec_caps,

				       &stream->timing, bw_range);

				       &stream->timing, dc_link_get_highest_encoding_format(stream->link), bw_range);



	return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16;

}

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

+18 −0
Original line number Diff line number Diff line
@@ -314,6 +314,24 @@ const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link) 
	return link->dc->link_srv->dp_get_verified_link_cap(link);

}



enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link)

{

	if (dc_is_dp_signal(link->connector_signal)) {

		if (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_DVI_DONGLE &&

				link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE)

			return DC_LINK_ENCODING_HDMI_TMDS;

		else if (link->dc->link_srv->dp_get_encoding_format(&link->verified_link_cap) ==

				DP_8b_10b_ENCODING)

			return DC_LINK_ENCODING_DP_8b_10b;

		else if (link->dc->link_srv->dp_get_encoding_format(&link->verified_link_cap) ==

				DP_128b_132b_ENCODING)

			return DC_LINK_ENCODING_DP_128b_132b;

	} else if (dc_is_hdmi_signal(link->connector_signal)) {

	}



	return DC_LINK_ENCODING_UNSPECIFIED;

}



bool dc_link_is_dp_sink_present(struct dc_link *link)

{

	return link->dc->link_srv->dp_is_sink_present(link);

drivers/gpu/drm/amd/display/dc/dc.h

+11 −1
Original line number Diff line number Diff line
@@ -1415,7 +1415,9 @@ void dc_set_disable_128b_132b_stream_overhead(bool disable); 
/* The function returns minimum bandwidth required to drive a given timing

 * return - minimum required timing bandwidth in kbps.

 */

uint32_t dc_bandwidth_in_kbps_from_timing(const struct dc_crtc_timing *timing);

uint32_t dc_bandwidth_in_kbps_from_timing(

		const struct dc_crtc_timing *timing,

		const enum dc_link_encoding_format link_encoding);



/* Link Interfaces */

/*
@@ -1853,6 +1855,14 @@ enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 
 */

const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link);



/* Get the highest encoding format that the link supports; highest meaning the

 * encoding format which supports the maximum bandwidth.

 *

 * @link - a link with DP RX connection

 * return - highest encoding format link supports.

 */

enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link);



/* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected

 * to a link with dp connector signal type.

 * @link - a link with dp connector signal type

drivers/gpu/drm/amd/display/dc/dc_dsc.h

+2 −0
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ bool dc_dsc_compute_bandwidth_range( 
		uint32_t max_bpp_x16,

		const struct dsc_dec_dpcd_caps *dsc_sink_caps,

		const struct dc_crtc_timing *timing,

		const enum dc_link_encoding_format link_encoding,

		struct dc_dsc_bw_range *range);



bool dc_dsc_compute_config(
@@ -81,6 +82,7 @@ bool dc_dsc_compute_config( 
		const struct dc_dsc_config_options *options,

		uint32_t target_bandwidth_kbps,

		const struct dc_crtc_timing *timing,

		const enum dc_link_encoding_format link_encoding,

		struct dc_dsc_config *dsc_cfg);



uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing,