drm/amdgpu: add SMUIO 9.0 register headers (63d311d9) · Commits · jan.koester / Linux

drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h

0 → 100644

+100 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (C) 2017 Advanced Micro Devices, Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included
		* in all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
		* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
		* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
		* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
		*/
		#ifndef _smuio_9_0_DEFAULT_HEADER
		#define _smuio_9_0_DEFAULT_HEADER


		// addressBlock: smuio_smuio_SmuSmuioDec
		#define mmROM_CNTL_DEFAULT 0x00000000
		#define mmROM_STATUS_DEFAULT 0x00000000
		#define mmCGTT_ROM_CLK_CTRL0_DEFAULT 0xc0000100
		#define mmROM_INDEX_DEFAULT 0x00000000
		#define mmROM_DATA_DEFAULT 0x00000000
		#define mmROM_START_DEFAULT 0x00000000
		#define mmROM_SW_CNTL_DEFAULT 0x00000000
		#define mmROM_SW_STATUS_DEFAULT 0x00000000
		#define mmROM_SW_COMMAND_DEFAULT 0x00000000
		#define mmROM_SW_DATA_1_DEFAULT 0x00000000
		#define mmROM_SW_DATA_2_DEFAULT 0x00000000
		#define mmROM_SW_DATA_3_DEFAULT 0x00000000
		#define mmROM_SW_DATA_4_DEFAULT 0x00000000
		#define mmROM_SW_DATA_5_DEFAULT 0x00000000
		#define mmROM_SW_DATA_6_DEFAULT 0x00000000
		#define mmROM_SW_DATA_7_DEFAULT 0x00000000
		#define mmROM_SW_DATA_8_DEFAULT 0x00000000
		#define mmROM_SW_DATA_9_DEFAULT 0x00000000
		#define mmROM_SW_DATA_10_DEFAULT 0x00000000
		#define mmROM_SW_DATA_11_DEFAULT 0x00000000
		#define mmROM_SW_DATA_12_DEFAULT 0x00000000
		#define mmROM_SW_DATA_13_DEFAULT 0x00000000
		#define mmROM_SW_DATA_14_DEFAULT 0x00000000
		#define mmROM_SW_DATA_15_DEFAULT 0x00000000
		#define mmROM_SW_DATA_16_DEFAULT 0x00000000
		#define mmROM_SW_DATA_17_DEFAULT 0x00000000
		#define mmROM_SW_DATA_18_DEFAULT 0x00000000
		#define mmROM_SW_DATA_19_DEFAULT 0x00000000
		#define mmROM_SW_DATA_20_DEFAULT 0x00000000
		#define mmROM_SW_DATA_21_DEFAULT 0x00000000
		#define mmROM_SW_DATA_22_DEFAULT 0x00000000
		#define mmROM_SW_DATA_23_DEFAULT 0x00000000
		#define mmROM_SW_DATA_24_DEFAULT 0x00000000
		#define mmROM_SW_DATA_25_DEFAULT 0x00000000
		#define mmROM_SW_DATA_26_DEFAULT 0x00000000
		#define mmROM_SW_DATA_27_DEFAULT 0x00000000
		#define mmROM_SW_DATA_28_DEFAULT 0x00000000
		#define mmROM_SW_DATA_29_DEFAULT 0x00000000
		#define mmROM_SW_DATA_30_DEFAULT 0x00000000
		#define mmROM_SW_DATA_31_DEFAULT 0x00000000
		#define mmROM_SW_DATA_32_DEFAULT 0x00000000
		#define mmROM_SW_DATA_33_DEFAULT 0x00000000
		#define mmROM_SW_DATA_34_DEFAULT 0x00000000
		#define mmROM_SW_DATA_35_DEFAULT 0x00000000
		#define mmROM_SW_DATA_36_DEFAULT 0x00000000
		#define mmROM_SW_DATA_37_DEFAULT 0x00000000
		#define mmROM_SW_DATA_38_DEFAULT 0x00000000
		#define mmROM_SW_DATA_39_DEFAULT 0x00000000
		#define mmROM_SW_DATA_40_DEFAULT 0x00000000
		#define mmROM_SW_DATA_41_DEFAULT 0x00000000
		#define mmROM_SW_DATA_42_DEFAULT 0x00000000
		#define mmROM_SW_DATA_43_DEFAULT 0x00000000
		#define mmROM_SW_DATA_44_DEFAULT 0x00000000
		#define mmROM_SW_DATA_45_DEFAULT 0x00000000
		#define mmROM_SW_DATA_46_DEFAULT 0x00000000
		#define mmROM_SW_DATA_47_DEFAULT 0x00000000
		#define mmROM_SW_DATA_48_DEFAULT 0x00000000
		#define mmROM_SW_DATA_49_DEFAULT 0x00000000
		#define mmROM_SW_DATA_50_DEFAULT 0x00000000
		#define mmROM_SW_DATA_51_DEFAULT 0x00000000
		#define mmROM_SW_DATA_52_DEFAULT 0x00000000
		#define mmROM_SW_DATA_53_DEFAULT 0x00000000
		#define mmROM_SW_DATA_54_DEFAULT 0x00000000
		#define mmROM_SW_DATA_55_DEFAULT 0x00000000
		#define mmROM_SW_DATA_56_DEFAULT 0x00000000
		#define mmROM_SW_DATA_57_DEFAULT 0x00000000
		#define mmROM_SW_DATA_58_DEFAULT 0x00000000
		#define mmROM_SW_DATA_59_DEFAULT 0x00000000
		#define mmROM_SW_DATA_60_DEFAULT 0x00000000
		#define mmROM_SW_DATA_61_DEFAULT 0x00000000
		#define mmROM_SW_DATA_62_DEFAULT 0x00000000
		#define mmROM_SW_DATA_63_DEFAULT 0x00000000
		#define mmROM_SW_DATA_64_DEFAULT 0x00000000

		#endif

drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_offset.h

0 → 100644

+175 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (C) 2017 Advanced Micro Devices, Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included
		* in all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
		* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
		* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
		* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
		*/
		#ifndef _smuio_9_0_OFFSET_HEADER
		#define _smuio_9_0_OFFSET_HEADER



		// addressBlock: smuio_smuio_SmuSmuioDec
		// base address: 0x5a000
		#define mmROM_CNTL 0x0024
		#define mmROM_CNTL_BASE_IDX 0
		#define mmROM_STATUS 0x0026
		#define mmROM_STATUS_BASE_IDX 0
		#define mmCGTT_ROM_CLK_CTRL0 0x0027
		#define mmCGTT_ROM_CLK_CTRL0_BASE_IDX 0
		#define mmROM_INDEX 0x0028
		#define mmROM_INDEX_BASE_IDX 0
		#define mmROM_DATA 0x0029
		#define mmROM_DATA_BASE_IDX 0
		#define mmROM_START 0x002a
		#define mmROM_START_BASE_IDX 0
		#define mmROM_SW_CNTL 0x002b
		#define mmROM_SW_CNTL_BASE_IDX 0
		#define mmROM_SW_STATUS 0x002c
		#define mmROM_SW_STATUS_BASE_IDX 0
		#define mmROM_SW_COMMAND 0x002d
		#define mmROM_SW_COMMAND_BASE_IDX 0
		#define mmROM_SW_DATA_1 0x002e
		#define mmROM_SW_DATA_1_BASE_IDX 0
		#define mmROM_SW_DATA_2 0x002f
		#define mmROM_SW_DATA_2_BASE_IDX 0
		#define mmROM_SW_DATA_3 0x0030
		#define mmROM_SW_DATA_3_BASE_IDX 0
		#define mmROM_SW_DATA_4 0x0031
		#define mmROM_SW_DATA_4_BASE_IDX 0
		#define mmROM_SW_DATA_5 0x0032
		#define mmROM_SW_DATA_5_BASE_IDX 0
		#define mmROM_SW_DATA_6 0x0033
		#define mmROM_SW_DATA_6_BASE_IDX 0
		#define mmROM_SW_DATA_7 0x0034
		#define mmROM_SW_DATA_7_BASE_IDX 0
		#define mmROM_SW_DATA_8 0x0035
		#define mmROM_SW_DATA_8_BASE_IDX 0
		#define mmROM_SW_DATA_9 0x0036
		#define mmROM_SW_DATA_9_BASE_IDX 0
		#define mmROM_SW_DATA_10 0x0037
		#define mmROM_SW_DATA_10_BASE_IDX 0
		#define mmROM_SW_DATA_11 0x0038
		#define mmROM_SW_DATA_11_BASE_IDX 0
		#define mmROM_SW_DATA_12 0x0039
		#define mmROM_SW_DATA_12_BASE_IDX 0
		#define mmROM_SW_DATA_13 0x003a
		#define mmROM_SW_DATA_13_BASE_IDX 0
		#define mmROM_SW_DATA_14 0x003b
		#define mmROM_SW_DATA_14_BASE_IDX 0
		#define mmROM_SW_DATA_15 0x003c
		#define mmROM_SW_DATA_15_BASE_IDX 0
		#define mmROM_SW_DATA_16 0x003d
		#define mmROM_SW_DATA_16_BASE_IDX 0
		#define mmROM_SW_DATA_17 0x003e
		#define mmROM_SW_DATA_17_BASE_IDX 0
		#define mmROM_SW_DATA_18 0x003f
		#define mmROM_SW_DATA_18_BASE_IDX 0
		#define mmROM_SW_DATA_19 0x0040
		#define mmROM_SW_DATA_19_BASE_IDX 0
		#define mmROM_SW_DATA_20 0x0041
		#define mmROM_SW_DATA_20_BASE_IDX 0
		#define mmROM_SW_DATA_21 0x0042
		#define mmROM_SW_DATA_21_BASE_IDX 0
		#define mmROM_SW_DATA_22 0x0043
		#define mmROM_SW_DATA_22_BASE_IDX 0
		#define mmROM_SW_DATA_23 0x0044
		#define mmROM_SW_DATA_23_BASE_IDX 0
		#define mmROM_SW_DATA_24 0x0045
		#define mmROM_SW_DATA_24_BASE_IDX 0
		#define mmROM_SW_DATA_25 0x0046
		#define mmROM_SW_DATA_25_BASE_IDX 0
		#define mmROM_SW_DATA_26 0x0047
		#define mmROM_SW_DATA_26_BASE_IDX 0
		#define mmROM_SW_DATA_27 0x0048
		#define mmROM_SW_DATA_27_BASE_IDX 0
		#define mmROM_SW_DATA_28 0x0049
		#define mmROM_SW_DATA_28_BASE_IDX 0
		#define mmROM_SW_DATA_29 0x004a
		#define mmROM_SW_DATA_29_BASE_IDX 0
		#define mmROM_SW_DATA_30 0x004b
		#define mmROM_SW_DATA_30_BASE_IDX 0
		#define mmROM_SW_DATA_31 0x004c
		#define mmROM_SW_DATA_31_BASE_IDX 0
		#define mmROM_SW_DATA_32 0x004d
		#define mmROM_SW_DATA_32_BASE_IDX 0
		#define mmROM_SW_DATA_33 0x004e
		#define mmROM_SW_DATA_33_BASE_IDX 0
		#define mmROM_SW_DATA_34 0x004f
		#define mmROM_SW_DATA_34_BASE_IDX 0
		#define mmROM_SW_DATA_35 0x0050
		#define mmROM_SW_DATA_35_BASE_IDX 0
		#define mmROM_SW_DATA_36 0x0051
		#define mmROM_SW_DATA_36_BASE_IDX 0
		#define mmROM_SW_DATA_37 0x0052
		#define mmROM_SW_DATA_37_BASE_IDX 0
		#define mmROM_SW_DATA_38 0x0053
		#define mmROM_SW_DATA_38_BASE_IDX 0
		#define mmROM_SW_DATA_39 0x0054
		#define mmROM_SW_DATA_39_BASE_IDX 0
		#define mmROM_SW_DATA_40 0x0055
		#define mmROM_SW_DATA_40_BASE_IDX 0
		#define mmROM_SW_DATA_41 0x0056
		#define mmROM_SW_DATA_41_BASE_IDX 0
		#define mmROM_SW_DATA_42 0x0057
		#define mmROM_SW_DATA_42_BASE_IDX 0
		#define mmROM_SW_DATA_43 0x0058
		#define mmROM_SW_DATA_43_BASE_IDX 0
		#define mmROM_SW_DATA_44 0x0059
		#define mmROM_SW_DATA_44_BASE_IDX 0
		#define mmROM_SW_DATA_45 0x005a
		#define mmROM_SW_DATA_45_BASE_IDX 0
		#define mmROM_SW_DATA_46 0x005b
		#define mmROM_SW_DATA_46_BASE_IDX 0
		#define mmROM_SW_DATA_47 0x005c
		#define mmROM_SW_DATA_47_BASE_IDX 0
		#define mmROM_SW_DATA_48 0x005d
		#define mmROM_SW_DATA_48_BASE_IDX 0
		#define mmROM_SW_DATA_49 0x005e
		#define mmROM_SW_DATA_49_BASE_IDX 0
		#define mmROM_SW_DATA_50 0x005f
		#define mmROM_SW_DATA_50_BASE_IDX 0
		#define mmROM_SW_DATA_51 0x0060
		#define mmROM_SW_DATA_51_BASE_IDX 0
		#define mmROM_SW_DATA_52 0x0061
		#define mmROM_SW_DATA_52_BASE_IDX 0
		#define mmROM_SW_DATA_53 0x0062
		#define mmROM_SW_DATA_53_BASE_IDX 0
		#define mmROM_SW_DATA_54 0x0063
		#define mmROM_SW_DATA_54_BASE_IDX 0
		#define mmROM_SW_DATA_55 0x0064
		#define mmROM_SW_DATA_55_BASE_IDX 0
		#define mmROM_SW_DATA_56 0x0065
		#define mmROM_SW_DATA_56_BASE_IDX 0
		#define mmROM_SW_DATA_57 0x0066
		#define mmROM_SW_DATA_57_BASE_IDX 0
		#define mmROM_SW_DATA_58 0x0067
		#define mmROM_SW_DATA_58_BASE_IDX 0
		#define mmROM_SW_DATA_59 0x0068
		#define mmROM_SW_DATA_59_BASE_IDX 0
		#define mmROM_SW_DATA_60 0x0069
		#define mmROM_SW_DATA_60_BASE_IDX 0
		#define mmROM_SW_DATA_61 0x006a
		#define mmROM_SW_DATA_61_BASE_IDX 0
		#define mmROM_SW_DATA_62 0x006b
		#define mmROM_SW_DATA_62_BASE_IDX 0
		#define mmROM_SW_DATA_63 0x006c
		#define mmROM_SW_DATA_63_BASE_IDX 0
		#define mmROM_SW_DATA_64 0x006d
		#define mmROM_SW_DATA_64_BASE_IDX 0

		#endif

drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h

0 → 100644

+258 −0

File added.

Preview size limit exceeded, changes collapsed.