Commit 659a4ab8 authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amdgpu: Use instance lookup table for GC 9.4.3 



Register accesses need to be based on physical instance on bare metal.
Pass the right instance using logical to physical instance lookup
table before accessing registers. Add a macro GET_INST to get the right
physical instance of an IP corresponding to a logical instance.

v2: fix gfx_v9_4_3_check_rlcg_range() (Alex)

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarLe Ma <Le.Ma@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5d30cbb4

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

+10 −10
Original line number Diff line number Diff line
@@ -279,8 +279,8 @@ static int kgd_gfx_v9_4_3_hqd_load(struct amdgpu_device *adev, void *mqd, 


	/* HQD registers extend to CP_HQD_AQL_DISPATCH_ID_HI */

	mqd_hqd = &m->cp_mqd_base_addr_lo;

	hqd_base = SOC15_REG_OFFSET(GC, inst, regCP_MQD_BASE_ADDR);

	hqd_end = SOC15_REG_OFFSET(GC, inst, regCP_HQD_AQL_DISPATCH_ID_HI);

	hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_MQD_BASE_ADDR);

	hqd_end = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_AQL_DISPATCH_ID_HI);



	for (reg = hqd_base; reg <= hqd_end; reg++)

		WREG32_RLC(reg, mqd_hqd[reg - hqd_base]);
@@ -289,7 +289,7 @@ static int kgd_gfx_v9_4_3_hqd_load(struct amdgpu_device *adev, void *mqd, 
	/* Activate doorbell logic before triggering WPTR poll. */

	data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,

			     CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);

	WREG32_RLC(SOC15_REG_OFFSET(GC, inst, regCP_HQD_PQ_DOORBELL_CONTROL),

	WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL),

				data);



	if (wptr) {
@@ -319,27 +319,27 @@ static int kgd_gfx_v9_4_3_hqd_load(struct amdgpu_device *adev, void *mqd, 
		guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);

		guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;



		WREG32_RLC(SOC15_REG_OFFSET(GC, inst, regCP_HQD_PQ_WPTR_LO),

		WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO),

		       lower_32_bits(guessed_wptr));

		WREG32_RLC(SOC15_REG_OFFSET(GC, inst, regCP_HQD_PQ_WPTR_HI),

		WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI),

		       upper_32_bits(guessed_wptr));

		WREG32_RLC(SOC15_REG_OFFSET(GC, inst, regCP_HQD_PQ_WPTR_POLL_ADDR),

		WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR),

		       lower_32_bits((uintptr_t)wptr));

		WREG32_RLC(SOC15_REG_OFFSET(GC, inst,

		WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

			regCP_HQD_PQ_WPTR_POLL_ADDR_HI),

			upper_32_bits((uintptr_t)wptr));

		WREG32(SOC15_REG_OFFSET(GC, inst, regCP_PQ_WPTR_POLL_CNTL1),

		WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1),

		       (uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id,

			       queue_id));

	}



	/* Start the EOP fetcher */

	WREG32_RLC(SOC15_REG_OFFSET(GC, inst, regCP_HQD_EOP_RPTR),

	WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR),

	       REG_SET_FIELD(m->cp_hqd_eop_rptr,

			     CP_HQD_EOP_RPTR, INIT_FETCHER, 1));



	data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);

	WREG32_RLC(SOC15_REG_OFFSET(GC, inst, regCP_HQD_ACTIVE), data);

	WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE), data);



	kgd_gfx_v9_release_queue(adev, inst);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

+193 −188

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

+73 −73
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ 


static u64 gfxhub_v1_2_get_mc_fb_offset(struct amdgpu_device *adev)

{

	return (u64)RREG32_SOC15(GC, 0, regMC_VM_FB_OFFSET) << 24;

	return (u64)RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_FB_OFFSET) << 24;

}



static void gfxhub_v1_2_setup_vm_pt_regs(struct amdgpu_device *adev,
@@ -48,12 +48,12 @@ static void gfxhub_v1_2_setup_vm_pt_regs(struct amdgpu_device *adev, 
	num_xcc = NUM_XCC(adev->gfx.xcc_mask);

	for (i = 0; i < num_xcc; i++) {

		hub = &adev->vmhub[AMDGPU_GFXHUB(i)];

		WREG32_SOC15_OFFSET(GC, i,

		WREG32_SOC15_OFFSET(GC, GET_INST(GC, i),

				    regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,

				    hub->ctx_addr_distance * vmid,

				    lower_32_bits(page_table_base));



		WREG32_SOC15_OFFSET(GC, i,

		WREG32_SOC15_OFFSET(GC, GET_INST(GC, i),

				    regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,

				    hub->ctx_addr_distance * vmid,

				    upper_32_bits(page_table_base));
@@ -79,31 +79,31 @@ static void gfxhub_v1_2_init_gart_aperture_regs(struct amdgpu_device *adev) 
	num_xcc = NUM_XCC(adev->gfx.xcc_mask);

	for (i = 0; i < num_xcc; i++) {

		if (adev->gmc.pdb0_bo) {

			WREG32_SOC15(GC, i,

			WREG32_SOC15(GC, GET_INST(GC, i),

				     regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,

				     (u32)(adev->gmc.fb_start >> 12));

			WREG32_SOC15(GC, i,

			WREG32_SOC15(GC, GET_INST(GC, i),

				     regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,

				     (u32)(adev->gmc.fb_start >> 44));



			WREG32_SOC15(GC, i,

			WREG32_SOC15(GC, GET_INST(GC, i),

				     regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,

				     (u32)(adev->gmc.gart_end >> 12));

			WREG32_SOC15(GC, i,

			WREG32_SOC15(GC, GET_INST(GC, i),

				     regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,

				     (u32)(adev->gmc.gart_end >> 44));

		} else {

			WREG32_SOC15(GC, i,

			WREG32_SOC15(GC, GET_INST(GC, i),

				     regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,

				     (u32)(adev->gmc.gart_start >> 12));

			WREG32_SOC15(GC, i,

			WREG32_SOC15(GC, GET_INST(GC, i),

				     regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,

				     (u32)(adev->gmc.gart_start >> 44));



			WREG32_SOC15(GC, i,

			WREG32_SOC15(GC, GET_INST(GC, i),

				     regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,

				     (u32)(adev->gmc.gart_end >> 12));

			WREG32_SOC15(GC, i,

			WREG32_SOC15(GC, GET_INST(GC, i),

				     regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,

				     (u32)(adev->gmc.gart_end >> 44));

		}
@@ -119,13 +119,13 @@ static void gfxhub_v1_2_init_system_aperture_regs(struct amdgpu_device *adev) 
	num_xcc = NUM_XCC(adev->gfx.xcc_mask);

	for (i = 0; i < num_xcc; i++) {

		/* Program the AGP BAR */

		WREG32_SOC15_RLC(GC, i, regMC_VM_AGP_BASE, 0);

		WREG32_SOC15_RLC(GC, i, regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);

		WREG32_SOC15_RLC(GC, i, regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);

		WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_BASE, 0);

		WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);

		WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);



		if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) {

			/* Program the system aperture low logical page number. */

			WREG32_SOC15_RLC(GC, i, regMC_VM_SYSTEM_APERTURE_LOW_ADDR,

			WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_LOW_ADDR,

				min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);



			if (adev->apu_flags & AMD_APU_IS_RAVEN2)
@@ -136,44 +136,44 @@ static void gfxhub_v1_2_init_system_aperture_regs(struct amdgpu_device *adev) 
				* aperture high address (add 1) to get rid of the VM

				* fault and hardware hang.

				*/

				WREG32_SOC15_RLC(GC, i,

				WREG32_SOC15_RLC(GC, GET_INST(GC, i),

						 regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

						 max((adev->gmc.fb_end >> 18) + 0x1,

						     adev->gmc.agp_end >> 18));

			else

				WREG32_SOC15_RLC(GC, i,

				WREG32_SOC15_RLC(GC, GET_INST(GC, i),

					regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

					max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);



			/* Set default page address. */

			value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);

			WREG32_SOC15(GC, i, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,

			WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,

				     (u32)(value >> 12));

			WREG32_SOC15(GC, i, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

			WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

				     (u32)(value >> 44));



			/* Program "protection fault". */

			WREG32_SOC15(GC, i, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,

			WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,

				     (u32)(adev->dummy_page_addr >> 12));

			WREG32_SOC15(GC, i, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,

			WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,

				     (u32)((u64)adev->dummy_page_addr >> 44));



			tmp = RREG32_SOC15(GC, i, regVM_L2_PROTECTION_FAULT_CNTL2);

			tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2);

			tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,

					    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);

			WREG32_SOC15(GC, i, regVM_L2_PROTECTION_FAULT_CNTL2, tmp);

			WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2, tmp);

		}



		/* In the case squeezing vram into GART aperture, we don't use

		 * FB aperture and AGP aperture. Disable them.

		 */

		if (adev->gmc.pdb0_bo) {

			WREG32_SOC15(GC, i, regMC_VM_FB_LOCATION_TOP, 0);

			WREG32_SOC15(GC, i, regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);

			WREG32_SOC15(GC, i, regMC_VM_AGP_TOP, 0);

			WREG32_SOC15(GC, i, regMC_VM_AGP_BOT, 0xFFFFFF);

			WREG32_SOC15(GC, i, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);

			WREG32_SOC15(GC, i, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);

			WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_TOP, 0);

			WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);

			WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_AGP_TOP, 0);

			WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_AGP_BOT, 0xFFFFFF);

			WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);

			WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);

		}

	}

}
@@ -186,7 +186,7 @@ static void gfxhub_v1_2_init_tlb_regs(struct amdgpu_device *adev) 
	num_xcc = NUM_XCC(adev->gfx.xcc_mask);

	for (i = 0; i < num_xcc; i++) {

		/* Setup TLB control */

		tmp = RREG32_SOC15(GC, i, regMC_VM_MX_L1_TLB_CNTL);

		tmp = RREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL);



		tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

				    ENABLE_L1_TLB, 1);
@@ -200,7 +200,7 @@ static void gfxhub_v1_2_init_tlb_regs(struct amdgpu_device *adev) 
				    MTYPE, MTYPE_UC);/* XXX for emulation. */

		tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);



		WREG32_SOC15_RLC(GC, i, regMC_VM_MX_L1_TLB_CNTL, tmp);

		WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL, tmp);

	}

}
@@ -212,7 +212,7 @@ static void gfxhub_v1_2_init_cache_regs(struct amdgpu_device *adev) 
	num_xcc = NUM_XCC(adev->gfx.xcc_mask);

	for (i = 0; i < num_xcc; i++) {

		/* Setup L2 cache */

		tmp = RREG32_SOC15(GC, i, regVM_L2_CNTL);

		tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);

		/* XXX for emulation, Refer to closed source code.*/
@@ -221,12 +221,12 @@ static void gfxhub_v1_2_init_cache_regs(struct amdgpu_device *adev) 
		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

		WREG32_SOC15_RLC(GC, i, regVM_L2_CNTL, tmp);

		WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL, tmp);



		tmp = RREG32_SOC15(GC, i, regVM_L2_CNTL2);

		tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL2);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

		WREG32_SOC15_RLC(GC, i, regVM_L2_CNTL2, tmp);

		WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL2, tmp);



		tmp = regVM_L2_CNTL3_DEFAULT;

		if (adev->gmc.translate_further) {
@@ -238,7 +238,7 @@ static void gfxhub_v1_2_init_cache_regs(struct amdgpu_device *adev) 
			tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

					    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);

		}

		WREG32_SOC15_RLC(GC, i, regVM_L2_CNTL3, tmp);

		WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL3, tmp);



		tmp = regVM_L2_CNTL4_DEFAULT;

		if (adev->gmc.xgmi.connected_to_cpu) {
@@ -248,7 +248,7 @@ static void gfxhub_v1_2_init_cache_regs(struct amdgpu_device *adev) 
			tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

			tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

		}

		WREG32_SOC15_RLC(GC, i, regVM_L2_CNTL4, tmp);

		WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL4, tmp);

	}

}
@@ -259,7 +259,7 @@ static void gfxhub_v1_2_enable_system_domain(struct amdgpu_device *adev) 


	num_xcc = NUM_XCC(adev->gfx.xcc_mask);

	for (i = 0; i < num_xcc; i++) {

		tmp = RREG32_SOC15(GC, i, regVM_CONTEXT0_CNTL);

		tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,

				adev->gmc.vmid0_page_table_depth);
@@ -267,7 +267,7 @@ static void gfxhub_v1_2_enable_system_domain(struct amdgpu_device *adev) 
				adev->gmc.vmid0_page_table_block_size);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,

				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);

		WREG32_SOC15(GC, i, regVM_CONTEXT0_CNTL, tmp);

		WREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL, tmp);

	}

}
@@ -277,23 +277,23 @@ static void gfxhub_v1_2_disable_identity_aperture(struct amdgpu_device *adev) 


	num_xcc = NUM_XCC(adev->gfx.xcc_mask);

	for (i = 0; i < num_xcc; i++) {

		WREG32_SOC15(GC, i,

		WREG32_SOC15(GC, GET_INST(GC, i),

			     regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,

			     0XFFFFFFFF);

		WREG32_SOC15(GC, i,

		WREG32_SOC15(GC, GET_INST(GC, i),

			     regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,

			     0x0000000F);



		WREG32_SOC15(GC, i,

		WREG32_SOC15(GC, GET_INST(GC, i),

			     regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,

			     0);

		WREG32_SOC15(GC, i,

		WREG32_SOC15(GC, GET_INST(GC, i),

			     regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,

			     0);



		WREG32_SOC15(GC, i,

		WREG32_SOC15(GC, GET_INST(GC, i),

			     regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);

		WREG32_SOC15(GC, i,

		WREG32_SOC15(GC, GET_INST(GC, i),

			     regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);

	}

}
@@ -316,7 +316,7 @@ static void gfxhub_v1_2_setup_vmid_config(struct amdgpu_device *adev) 
	for (j = 0; j < num_xcc; j++) {

		hub = &adev->vmhub[AMDGPU_GFXHUB(j)];

		for (i = 0; i <= 14; i++) {

			tmp = RREG32_SOC15_OFFSET(GC, j, regVM_CONTEXT1_CNTL, i);

			tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL, i);

			tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

			tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

					    num_level);
@@ -348,19 +348,19 @@ static void gfxhub_v1_2_setup_vmid_config(struct amdgpu_device *adev) 
					    !adev->gmc.noretry ||

					    adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ||

					    adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3));

			WREG32_SOC15_OFFSET(GC, j, regVM_CONTEXT1_CNTL,

			WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL,

					    i * hub->ctx_distance, tmp);

			WREG32_SOC15_OFFSET(GC, j,

			WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

					    regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,

					    i * hub->ctx_addr_distance, 0);

			WREG32_SOC15_OFFSET(GC, j,

			WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

					    regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,

					    i * hub->ctx_addr_distance, 0);

			WREG32_SOC15_OFFSET(GC, j,

			WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

					    regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,

					    i * hub->ctx_addr_distance,

					    lower_32_bits(adev->vm_manager.max_pfn - 1));

			WREG32_SOC15_OFFSET(GC, j,

			WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),

					    regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,

					    i * hub->ctx_addr_distance,

					    upper_32_bits(adev->vm_manager.max_pfn - 1));
@@ -378,9 +378,9 @@ static void gfxhub_v1_2_program_invalidation(struct amdgpu_device *adev) 
		hub = &adev->vmhub[AMDGPU_GFXHUB(j)];



		for (i = 0 ; i < 18; ++i) {

			WREG32_SOC15_OFFSET(GC, j, regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,

			WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,

					    i * hub->eng_addr_distance, 0xffffffff);

			WREG32_SOC15_OFFSET(GC, j, regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,

			WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,

					    i * hub->eng_addr_distance, 0x1f);

		}

	}
@@ -398,9 +398,9 @@ static int gfxhub_v1_2_gart_enable(struct amdgpu_device *adev) 
		 * VF copy registers so vbios post doesn't program them, for

		 * SRIOV driver need to program them

		 */

			WREG32_SOC15_RLC(GC, i, regMC_VM_FB_LOCATION_BASE,

			WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_BASE,

				     adev->gmc.vram_start >> 24);

			WREG32_SOC15_RLC(GC, i, regMC_VM_FB_LOCATION_TOP,

			WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_TOP,

				     adev->gmc.vram_end >> 24);

		}

	}
@@ -432,23 +432,23 @@ static void gfxhub_v1_2_gart_disable(struct amdgpu_device *adev) 
		hub = &adev->vmhub[AMDGPU_GFXHUB(j)];

		/* Disable all tables */

		for (i = 0; i < 16; i++)

			WREG32_SOC15_OFFSET(GC, j, regVM_CONTEXT0_CNTL,

			WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT0_CNTL,

					    i * hub->ctx_distance, 0);



		/* Setup TLB control */

		tmp = RREG32_SOC15(GC, j, regMC_VM_MX_L1_TLB_CNTL);

		tmp = RREG32_SOC15(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL);

		tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

		tmp = REG_SET_FIELD(tmp,

					MC_VM_MX_L1_TLB_CNTL,

					ENABLE_ADVANCED_DRIVER_MODEL,

					0);

		WREG32_SOC15_RLC(GC, j, regMC_VM_MX_L1_TLB_CNTL, tmp);

		WREG32_SOC15_RLC(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL, tmp);



		/* Setup L2 cache */

		tmp = RREG32_SOC15(GC, j, regVM_L2_CNTL);

		tmp = RREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);

		WREG32_SOC15(GC, j, regVM_L2_CNTL, tmp);

		WREG32_SOC15(GC, j, regVM_L2_CNTL3, 0);

		WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL, tmp);

		WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL3, 0);

	}

}
@@ -466,7 +466,7 @@ static void gfxhub_v1_2_set_fault_enable_default(struct amdgpu_device *adev, 


	num_xcc = NUM_XCC(adev->gfx.xcc_mask);

	for (i = 0; i < num_xcc; i++) {

		tmp = RREG32_SOC15(GC, i, regVM_L2_PROTECTION_FAULT_CNTL);

		tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL);

		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);

		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
@@ -497,7 +497,7 @@ static void gfxhub_v1_2_set_fault_enable_default(struct amdgpu_device *adev, 
			tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

					CRASH_ON_RETRY_FAULT, 1);

		}

		WREG32_SOC15(GC, i, regVM_L2_PROTECTION_FAULT_CNTL, tmp);

		WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL, tmp);

	}

}
@@ -511,24 +511,24 @@ static void gfxhub_v1_2_init(struct amdgpu_device *adev) 
		hub = &adev->vmhub[AMDGPU_GFXHUB(i)];



		hub->ctx0_ptb_addr_lo32 =

			SOC15_REG_OFFSET(GC, i,

			SOC15_REG_OFFSET(GC, GET_INST(GC, i),

				regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);

		hub->ctx0_ptb_addr_hi32 =

			SOC15_REG_OFFSET(GC, i,

			SOC15_REG_OFFSET(GC, GET_INST(GC, i),

				regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);

		hub->vm_inv_eng0_sem =

			SOC15_REG_OFFSET(GC, i, regVM_INVALIDATE_ENG0_SEM);

			SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_SEM);

		hub->vm_inv_eng0_req =

			SOC15_REG_OFFSET(GC, i, regVM_INVALIDATE_ENG0_REQ);

			SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_REQ);

		hub->vm_inv_eng0_ack =

			SOC15_REG_OFFSET(GC, i, regVM_INVALIDATE_ENG0_ACK);

			SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_ACK);

		hub->vm_context0_cntl =

			SOC15_REG_OFFSET(GC, i, regVM_CONTEXT0_CNTL);

			SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL);

		hub->vm_l2_pro_fault_status =

			SOC15_REG_OFFSET(GC, i,

			SOC15_REG_OFFSET(GC, GET_INST(GC, i),

				regVM_L2_PROTECTION_FAULT_STATUS);

		hub->vm_l2_pro_fault_cntl =

			SOC15_REG_OFFSET(GC, i, regVM_L2_PROTECTION_FAULT_CNTL);

			SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL);



		hub->ctx_distance = regVM_CONTEXT1_CNTL -

				regVM_CONTEXT0_CNTL;
@@ -551,9 +551,9 @@ static int gfxhub_v1_2_get_xgmi_info(struct amdgpu_device *adev) 
	u32 max_region;

	u64 seg_size;



	xgmi_lfb_cntl = RREG32_SOC15(GC, 0, regMC_VM_XGMI_LFB_CNTL);

	xgmi_lfb_cntl = RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_XGMI_LFB_CNTL);

	seg_size = REG_GET_FIELD(

		RREG32_SOC15(GC, 0, regMC_VM_XGMI_LFB_SIZE),

		RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_XGMI_LFB_SIZE),

		MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;

	max_region =

		REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);

drivers/gpu/drm/amd/amdgpu/soc15_common.h

+3 −0
Original line number Diff line number Diff line
@@ -24,6 +24,9 @@ 
#ifndef __SOC15_COMMON_H__

#define __SOC15_COMMON_H__



/* GET_INST returns the physical instance corresponding to a logical instance */

#define GET_INST(ip, inst) (adev->ip_map.logical_to_dev_inst? adev->ip_map.logical_to_dev_inst(adev, ip##_HWIP, inst): inst)



/* Register Access Macros */

#define SOC15_REG_OFFSET(ip, inst, reg)	(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)

#define SOC15_REG_OFFSET1(ip, inst, reg, offset) \