Commit 6655744d authored by Neil Armstrong's avatar Neil Armstrong Committed by Jerome Brunet
Browse files

dt-bindings: clk: g12a-aoclkc: expose all clock ids 

Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.

This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.

It was decided to move every g12a-aoclkc ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.

[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/



Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-10-38172d17c27a@linaro.org


Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent b1262497

drivers/clk/meson/g12a-aoclk.h

+0 −17
Original line number Diff line number Diff line
@@ -7,23 +7,6 @@ 
#ifndef __G12A_AOCLKC_H

#define __G12A_AOCLKC_H



/*

 * CLKID index values

 *

 * These indices are entirely contrived and do not map onto the hardware.

 * It has now been decided to expose everything by default in the DT header:

 * include/dt-bindings/clock/g12a-aoclkc.h. Only the clocks ids we don't want

 * to expose, such as the internal muxes and dividers of composite clocks,

 * will remain defined here.

 */

#define CLKID_AO_SAR_ADC_DIV	17

#define CLKID_AO_32K_PRE	20

#define CLKID_AO_32K_DIV	21

#define CLKID_AO_32K_SEL	22

#define CLKID_AO_CEC_PRE	24

#define CLKID_AO_CEC_DIV	25

#define CLKID_AO_CEC_SEL	26



#include <dt-bindings/clock/g12a-aoclkc.h>

#include <dt-bindings/reset/g12a-aoclkc.h>

include/dt-bindings/clock/g12a-aoclkc.h

+7 −0
Original line number Diff line number Diff line
@@ -26,10 +26,17 @@ 
#define CLKID_AO_M4_FCLK	13

#define CLKID_AO_M4_HCLK	14

#define CLKID_AO_CLK81		15

#define CLKID_AO_SAR_ADC_DIV	17

#define CLKID_AO_SAR_ADC_SEL	16

#define CLKID_AO_SAR_ADC_CLK	18

#define CLKID_AO_CTS_OSCIN	19

#define CLKID_AO_32K_PRE	20

#define CLKID_AO_32K_DIV	21

#define CLKID_AO_32K_SEL	22

#define CLKID_AO_32K		23

#define CLKID_AO_CEC_PRE	24

#define CLKID_AO_CEC_DIV	25

#define CLKID_AO_CEC_SEL	26

#define CLKID_AO_CEC		27

#define CLKID_AO_CTS_RTC_OSCIN	28