Skip to content
Commit 6671507f authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by Stephen Boyd
Browse files

clk: aspeed: Handle inverse polarity of USB port 1 clock gate



The USB port 1 clock gate control has an inversed polarity
from all the other clock gates in the chip. This makes the
aspeed_clk_{enable,disable} functions honor the flag
CLK_GATE_SET_TO_DISABLE and set that flag appropriately
so it's set for all clocks except USB port 1.

Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: default avatarJoel Stanley <joel@jms.id.au>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent accf475a
Loading
Loading
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment