Commit 685b4d81 authored by Isabel Zhang's avatar Isabel Zhang Committed by Alex Deucher
Browse files

drm/amd/display: Force prefetch mode to 0 



[Why]
On APU should be always using prefetch mode 0.
Currently, sometimes prefetch mode 1 is being
used causing system to hard hang due to
minTTUVBlank being too low.

[How]
Any ASIC running DCN21 will by default allow
self refresh and mclk switch. This sets both
min and max prefetch mode to 0 by default.

Signed-off-by: default avatarIsabel Zhang <isabel.zhang@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 850d2fcf

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

+3 −1
Original line number Diff line number Diff line
@@ -301,7 +301,9 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { 
	.xfc_bus_transport_time_us = 4,

	.xfc_xbuf_latency_tolerance_us = 4,

	.use_urgent_burst_bw = 1,

	.num_states = 8

	.num_states = 8,

	.allow_dram_self_refresh_or_dram_clock_change_in_vblank

			= dm_allow_self_refresh_and_mclk_switch

};



#ifndef MAX