Commit 69e51448 authored by Jonathan Cameron's avatar Jonathan Cameron
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iio: dac: ad7303: Fix alignment for DMA safety 



____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Fixes: f8347824 ("iio:dac: Add support for the AD7303")
Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: default avatarNuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-58-jic23@kernel.org
parent 8482468b

drivers/iio/dac/ad7303.c

+2 −2
Original line number Diff line number Diff line
@@ -44,10 +44,10 @@ struct ad7303_state { 


	struct mutex lock;

	/*

	 * DMA (thus cache coherency maintenance) requires the

	 * DMA (thus cache coherency maintenance) may require the

	 * transfer buffers to live in their own cache lines.

	 */

	__be16 data ____cacheline_aligned;

	__be16 data __aligned(IIO_DMA_MINALIGN);

};



static int ad7303_write(struct ad7303_state *st, unsigned int chan,