Unverified Commit 6a023136 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'dt64-cleanup-6.5' of... 

Merge tag 'dt64-cleanup-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt

Minor improvements in ARM64 DTS for v6.5

Mostly minor improvements to fix dtbs_check warnings:
1. mba6ulx: use non-deprecated property for GPIO keys wake-up,
2. Add missing cache properties (APM, Amazon, HiSilicon, Realtek,
   Synaptics, AllWinner, Microchip).

Few older minor and major fixes which were waiting on mailing lists for
longer time for Microchip SparX-5:
1. Fix secondary CPU bring-up and crash when talking to PSCI on reference
   boards (Robert Marko),
2. Simplify CPU address-cells (Robert Marko),
3. Align pinctrl node names with bindings (Michael Walle).

* tag 'dt64-cleanup-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt:
  arm64: dts: sparx5: rename pinctrl nodes
  arm64: dts: microchip: sparx5: correct CPU address-cells
  arm64: dts: microchip: sparx5: do not use PSCI on reference boards
  arm64: dts: microchip: add missing cache properties
  arm64: dts: allwinner: a64: add missing cache properties
  arm64: dts: synaptics: add missing cache properties
  arm64: dts: realtek: add missing cache properties
  arm64: dts: hisilicon: add missing cache properties
  arm64: dts: amazon: add missing cache properties
  arm64: dts: apm: add missing cache properties
  arm64: dts: mba6ulx: correct GPIO keys wakeup

Link: https://lore.kernel.org/r/20230517131255.471002-1-krzysztof.kozlowski@linaro.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 44c026a7 d5e64404

arch/arm/boot/dts/mba6ulx.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ power-button { 
			label = "POWER";

			linux,code = <KEY_POWER>;

			gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;

			gpio-key,wakeup;

			wakeup-source;

		};

	};

arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -93,6 +93,7 @@ cpu3: cpu@3 { 
		L2: l2-cache {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};

arch/arm64/boot/dts/amazon/alpine-v3.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -250,6 +250,7 @@ cluster0_l2: cache@0 { 
			cache-line-size = <64>;

			cache-sets = <2048>;

			cache-level = <2>;

			cache-unified;

		};



		cluster1_l2: cache@100 {
@@ -258,6 +259,7 @@ cluster1_l2: cache@100 { 
			cache-line-size = <64>;

			cache-sets = <2048>;

			cache-level = <2>;

			cache-unified;

		};



		cluster2_l2: cache@200 {
@@ -266,6 +268,7 @@ cluster2_l2: cache@200 { 
			cache-line-size = <64>;

			cache-sets = <2048>;

			cache-level = <2>;

			cache-unified;

		};



		cluster3_l2: cache@300 {
@@ -274,6 +277,7 @@ cluster3_l2: cache@300 { 
			cache-line-size = <64>;

			cache-sets = <2048>;

			cache-level = <2>;

			cache-unified;

		};



	};

arch/arm64/boot/dts/apm/apm-shadowcat.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -97,15 +97,23 @@ cpu@301 { 
		};

		xgene_L2_0: l2-cache-0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

		xgene_L2_1: l2-cache-1 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

		xgene_L2_2: l2-cache-2 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

		xgene_L2_3: l2-cache-3 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};

arch/arm64/boot/dts/apm/apm-storm.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -81,15 +81,23 @@ cpu@301 { 
		};

		xgene_L2_0: l2-cache-0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

		xgene_L2_1: l2-cache-1 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

		xgene_L2_2: l2-cache-2 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

		xgene_L2_3: l2-cache-3 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};