Unverified Commit 6a4020b4 authored by Francesco Dolcini's avatar Francesco Dolcini Committed by Robert Foss
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drm/bridge: tc358768: fix PLL parameters computation 



According to Toshiba documentation the PLL input clock after the divider
should be not less than 4MHz, fix the PLL parameters computation
accordingly.

Fixes: ff1ca639 ("drm/bridge: Add tc358768 driver")
Signed-off-by: default avatarFrancesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: default avatarRobert Foss <rfoss@kernel.org>
Signed-off-by: default avatarRobert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20230427142934.55435-3-francesco@dolcini.it
parent 75a8aeac

drivers/gpu/drm/bridge/tc358768.c

+5 −1
Original line number Diff line number Diff line
@@ -335,13 +335,17 @@ static int tc358768_calc_pll(struct tc358768_priv *priv, 
		u32 fbd;



		for (fbd = 0; fbd < 512; ++fbd) {

			u32 pll, diff;

			u32 pll, diff, pll_in;



			pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor);



			if (pll >= max_pll || pll < min_pll)

				continue;



			pll_in = (u32)div_u64((u64)refclk, prd + 1);

			if (pll_in < 4000000)

				continue;



			diff = max(pll, target_pll) - min(pll, target_pll);



			if (diff < best_diff) {