Commit 6a623729 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915/execlists: Pull the render flush into breadcrumb emission 



In preparation for removing the manual EMIT_FLUSH prior to emitting the
breadcrumb implement the flush inline with writing the breadcrumb for
execlists. Using one command to both flush and write the breadcrumb is
naturally a tiny bit faster than splitting it into two.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181228153114.4948-1-chris@chris-wilson.co.uk
parent 95898ed6

drivers/gpu/drm/i915/intel_guc_submission.c

+2 −1
Original line number Diff line number Diff line
@@ -572,7 +572,8 @@ static void inject_preempt_context(struct work_struct *work) 
		if (engine->id == RCS) {

			cs = gen8_emit_ggtt_write_rcs(cs,

						      GUC_PREEMPT_FINISHED,

						      addr);

						      addr,

						      PIPE_CONTROL_CS_STALL);

		} else {

			cs = gen8_emit_ggtt_write(cs,

						  GUC_PREEMPT_FINISHED,

drivers/gpu/drm/i915/intel_lrc.c

+10 −2
Original line number Diff line number Diff line
@@ -2061,10 +2061,18 @@ static void gen8_emit_breadcrumb_rcs(struct i915_request *request, u32 *cs) 
	/* We're using qword write, seqno should be aligned to 8 bytes. */

	BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);



	cs = gen8_emit_ggtt_write_rcs(cs, request->global_seqno,

				      intel_hws_seqno_address(request->engine));

	cs = gen8_emit_ggtt_write_rcs(cs,

				      request->global_seqno,

				      intel_hws_seqno_address(request->engine),

				      PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |

				      PIPE_CONTROL_DEPTH_CACHE_FLUSH |

				      PIPE_CONTROL_DC_FLUSH_ENABLE |

				      PIPE_CONTROL_FLUSH_ENABLE |

				      PIPE_CONTROL_CS_STALL);



	*cs++ = MI_USER_INTERRUPT;

	*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;



	request->tail = intel_ring_offset(request, cs);

	assert_ring_tail_valid(request->ring, request->tail);

drivers/gpu/drm/i915/intel_ringbuffer.h

+2 −3
Original line number Diff line number Diff line
@@ -1003,7 +1003,7 @@ static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset) 
}



static inline u32 *

gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset)

gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)

{

	/* We're using qword write, offset should be aligned to 8 bytes. */

	GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
@@ -1013,8 +1013,7 @@ gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset) 
	 * following the batch.

	 */

	*cs++ = GFX_OP_PIPE_CONTROL(6);

	*cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL |

		PIPE_CONTROL_QW_WRITE;

	*cs++ = flags | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB;

	*cs++ = gtt_offset;

	*cs++ = 0;

	*cs++ = value;