Commit 6a7bdd89 authored by Laurent Pinchart's avatar Laurent Pinchart Committed by Mauro Carvalho Chehab
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media: v4l2-mediabus: Use structures to describe bus configuration 



The media bus configuration is specified through a set of flags, some of
which being mutually exclusive. This doesn't scale to express more
complex configurations. Improve the API by replacing the single flags
field in v4l2_mbus_config by a union of v4l2_mbus_config_* structures.
The flags themselves are still used in those structures, so they are
kept here. Drivers are however updated to use structure fields instead
of flags when already possible.

Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: default avatarSakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@kernel.org>
parent 44e756fa

drivers/gpu/ipu-v3/ipu-csi.c

+3 −3
Original line number Diff line number Diff line
@@ -357,11 +357,11 @@ static int fill_csi_bus_cfg(struct ipu_csi_bus_config *csicfg, 
	switch (mbus_cfg->type) {

	case V4L2_MBUS_PARALLEL:

		csicfg->ext_vsync = 1;

		csicfg->vsync_pol = (mbus_cfg->flags &

		csicfg->vsync_pol = (mbus_cfg->bus.parallel.flags &

				     V4L2_MBUS_VSYNC_ACTIVE_LOW) ? 1 : 0;

		csicfg->hsync_pol = (mbus_cfg->flags &

		csicfg->hsync_pol = (mbus_cfg->bus.parallel.flags &

				     V4L2_MBUS_HSYNC_ACTIVE_LOW) ? 1 : 0;

		csicfg->pixclk_pol = (mbus_cfg->flags &

		csicfg->pixclk_pol = (mbus_cfg->bus.parallel.flags &

				      V4L2_MBUS_PCLK_SAMPLE_FALLING) ? 1 : 0;

		csicfg->clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;

		break;

drivers/media/i2c/adv7180.c

+5 −3
Original line number Diff line number Diff line
@@ -784,7 +784,8 @@ static int adv7180_get_mbus_config(struct v4l2_subdev *sd, 


	if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {

		cfg->type = V4L2_MBUS_CSI2_DPHY;

		cfg->flags = V4L2_MBUS_CSI2_1_LANE |

		cfg->bus.mipi_csi2.num_data_lanes = 1;

		cfg->bus.mipi_csi2.flags =

				V4L2_MBUS_CSI2_CHANNEL_0 |

				V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;

	} else {
@@ -792,7 +793,8 @@ static int adv7180_get_mbus_config(struct v4l2_subdev *sd, 
		 * The ADV7180 sensor supports BT.601/656 output modes.

		 * The BT.656 is default and not yet configurable by s/w.

		 */

		cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |

		cfg->bus.parallel.flags = V4L2_MBUS_MASTER |

					  V4L2_MBUS_PCLK_SAMPLE_RISING |

					  V4L2_MBUS_DATA_ACTIVE_HIGH;

		cfg->type = V4L2_MBUS_BT656;

	}

drivers/media/i2c/adv748x/adv748x-csi2.c

+1 −17
Original line number Diff line number Diff line
@@ -222,23 +222,7 @@ static int adv748x_csi2_get_mbus_config(struct v4l2_subdev *sd, unsigned int pad 
		return -EINVAL;



	config->type = V4L2_MBUS_CSI2_DPHY;

	switch (tx->active_lanes) {

	case 1:

		config->flags = V4L2_MBUS_CSI2_1_LANE;

		break;



	case 2:

		config->flags = V4L2_MBUS_CSI2_2_LANE;

		break;



	case 3:

		config->flags = V4L2_MBUS_CSI2_3_LANE;

		break;



	case 4:

		config->flags = V4L2_MBUS_CSI2_4_LANE;

		break;

	}

	config->bus.mipi_csi2.num_data_lanes = tx->active_lanes;



	return 0;

}

drivers/media/i2c/ml86v7667.c

+3 −2
Original line number Diff line number Diff line
@@ -223,9 +223,10 @@ static int ml86v7667_get_mbus_config(struct v4l2_subdev *sd, 
				     unsigned int pad,

				     struct v4l2_mbus_config *cfg)

{

	cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |

		     V4L2_MBUS_DATA_ACTIVE_HIGH;

	cfg->type = V4L2_MBUS_BT656;

	cfg->bus.parallel.flags = V4L2_MBUS_MASTER |

				  V4L2_MBUS_PCLK_SAMPLE_RISING |

				  V4L2_MBUS_DATA_ACTIVE_HIGH;



	return 0;

}

drivers/media/i2c/mt9m001.c

+5 −3
Original line number Diff line number Diff line
@@ -695,10 +695,12 @@ static int mt9m001_get_mbus_config(struct v4l2_subdev *sd, 
				   struct v4l2_mbus_config *cfg)

{

	/* MT9M001 has all capture_format parameters fixed */

	cfg->flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |

		V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH |

		V4L2_MBUS_DATA_ACTIVE_HIGH | V4L2_MBUS_MASTER;

	cfg->type = V4L2_MBUS_PARALLEL;

	cfg->bus.parallel.flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |

				  V4L2_MBUS_HSYNC_ACTIVE_HIGH |

				  V4L2_MBUS_VSYNC_ACTIVE_HIGH |

				  V4L2_MBUS_DATA_ACTIVE_HIGH |

				  V4L2_MBUS_MASTER;



	return 0;

}