Loading arch/mips/kernel/traps.c +6 −6 Original line number Diff line number Diff line Loading @@ -927,12 +927,6 @@ asmlinkage void do_reserved(struct pt_regs *regs) (regs->cp0_cause & 0x7f) >> 2); } static asmlinkage void do_default_vi(void) { show_regs(get_irq_regs()); panic("Caught unexpected vectored interrupt."); } /* * Some MIPS CPUs can enable/disable for cache parity detection, but do * it different ways. Loading Loading @@ -1128,6 +1122,12 @@ void mips_srs_free(int set) clear_bit(set, &sr->sr_allocated); } static asmlinkage void do_default_vi(void) { show_regs(get_irq_regs()); panic("Caught unexpected vectored interrupt."); } static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) { unsigned long handler; Loading Loading
arch/mips/kernel/traps.c +6 −6 Original line number Diff line number Diff line Loading @@ -927,12 +927,6 @@ asmlinkage void do_reserved(struct pt_regs *regs) (regs->cp0_cause & 0x7f) >> 2); } static asmlinkage void do_default_vi(void) { show_regs(get_irq_regs()); panic("Caught unexpected vectored interrupt."); } /* * Some MIPS CPUs can enable/disable for cache parity detection, but do * it different ways. Loading Loading @@ -1128,6 +1122,12 @@ void mips_srs_free(int set) clear_bit(set, &sr->sr_allocated); } static asmlinkage void do_default_vi(void) { show_regs(get_irq_regs()); panic("Caught unexpected vectored interrupt."); } static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) { unsigned long handler; Loading